ZHCSFS6B July 2016 – June 2018 SN65DSI85-Q1
PRODUCTION DATA.
The SN65DSI85-Q1 device provides an IRQ pin that can indicate when certain errors occur on DSI. The IRQ output is enabled through the IRQ_EN bit (CSR 0xE0.0). Individual error conditions for DSI Channel A are enabled through the Channel A Error Enable bits (CSR 0xE1.7-2). Individual error conditions for DSI Channel B are enabled through the Channel B Error Enable bits (CSR 0xE2.7-2). The IRQ pin is asserted when an error occurs on DSI, the corresponding error enable bit is set, and the IRQ_EN bit is set. An error is cleared by writing a 1 to the corresponding error status bit.
NOTE
If the SOFT_RESET bit is set while the DSI video stream is active, some of the error status bits may be set.
NOTE
If the DSI video stream is stopped, some of the error status bits may be set. These error status bits should be cleared before restarting the video stream.
NOTE
If the DSI video stream starts before the device is configured, some of the error status bits may be set. TI recommends to start streaming after the device is correctly configured as recommended in the initialization sequence in the Initialization Setup section.