ZHCSFS6B July 2016 – June 2018 SN65DSI85-Q1
PRODUCTION DATA.
Address 0x0B is shown in Figure 21 and described in Table 10.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DSI_CLK_DIVIDER | Reserved | REFCLK_MULTIPLIER | |||||
| R/W-0000 | R/W-00 | ||||||
| LEGEND: R/W = Read/Write; R = Read only; W = Write only (reads return undetermined values); R/W1C = Read and Write 1 to Clear |
| BIT | FIELD | TYPE | RESET | DESCRIPTION |
|---|---|---|---|---|
| 7-3 | DSI_CLK_DIVIDER | R/W | 0000 | When CSR 0x0A.0 = 1, this field controls the divider used to generate the LVDS output clock from the MIPI D-PHY Channel A HS continuous clock. When CSR 0x0A.0 = 0, this field must be programmed to 00000.
00000: LVDS clock = source clock (default) 00001: Divide by 2 00010: Divide by 3 00011: Divide by 4 ... 10111: Divide by 24 11000: Divide by 25 11001–11111: Reserved |
| 2 | Reserved | Reserved | ||
| 1-0 | REFCLK_MULTIPLIER | R/W | 00 | When CSR 0x0A.0 = 0, this field controls the multiplier used to generate the LVDS output clock from the input REFCLK. When CSR 0x0A.0 = 1, this field must be programmed to 00.
00: LVDS clock = source clock (default) 01: Multiply by 2 10: Multiply by 3 11: Multiply by 4 |