ZHCSFS6B July 2016 – June 2018 SN65DSI85-Q1
PRODUCTION DATA.
Address 0x21 is shown in Figure 32 and described in Table 21.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reserved | CHA_ACTIVE_LINE_LENGTH_HIGH | ||||||
| R/W-0 | |||||||
| LEGEND: R/W = Read/Write; R = Read only; W = Write only (reads return undetermined values); R/W1C = Read and Write 1 to Clear |
| BIT | FIELD | TYPE | RESET | DESCRIPTION |
|---|---|---|---|---|
| 7–4 | Reserved | Reserved | ||
| 3-0 | CHA_ACTIVE_LINE_LENGTH_HIGH | R/W | 0 | When the SN65DSI85-Q1 is configured for a single DSI input, this field controls the length in pixels of the active horizontal line.
When configured for Dual DSI inputs in Odd/Even mode, this field controls the number of odd pixels in the active horizontal line that are received on DSI Channel A and output to LVDS Channel A in single LVDS Channel mode(CSR 0x18.4 = 1), Channel A and B in dual LVDS Channel mode(CSR 0x18.4 = 0) with DSI_CHANNEL_MODE set to 01 or 00(CSR 0x10.6:5). When configured for Dual DSI inputs in Left/Right mode, this field controls the number of left pixels in the active horizontal line that are received on DSI Channel A and output to LVDS Channel A. When configured for Dual DSI inputs in two stream mode, this field controls the number of pixels in the active horizontal line for the video stream received on DSI Channel A and output to LVDS Channel A. The value in this field is the upper 4 bits of the 12-bit value for the horizontal line length. Note: When the SN65DSI85-Q1 is configured for dual DSI inputs in Left/Right mode and LEFT_CROP field is programmed to a value other than 0x00, the CHA_ACTIVE_LINE_LENGTH_LOW/HIGH registers must be programmed to the number of active pixels in the Left portion of the line after LEFT_CROP has been applied. |