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ZHCSFS6B July 2016 – June 2018 SN65DSI85-Q1

PRODUCTION DATA.

封裝選項

機械數據 (封裝 | 引腳)

PAP|64
- MPQF071C

散熱焊盤機械數據 (封裝 | 引腳)

PAP|64
- PPTD318A

訂購信息

8.3.3 LVDS Output Formats

The SN65DSI85-Q1 device processes DSI packets and produces video data driven to the LVDS interface in an industry standard format. Single-Link LVDS and Dual-Link LVDS are supported by the SN65DSI85-Q1 device. When the LVDS output is implemented in a Dual-Link configuration, channel A carries the odd pixel data, and channel B carries the even pixel data. During conditions such as the default condition, and some video synchronization periods, where no video stream data is passing from the DSI input to the LVDS output, the SN65DSI85-Q1 device transmits zero value pixel data on the LVDS outputs while maintaining transmission of the vertical sync and horizontal sync status.

Figure 9 shows a Single-Link LVDS 18-bpp application.

Figure 10 shows a Dual-Link 24-bpp application using Format 2, controlled by CHA_24BPP_FORMAT1 (CSR 0x18.1) and CHB_24BPP_FORMAT1 (CSR 0x18.0). In data Format 2, the two MSB per color are transferred on the Y3P/N LVDS lane.

Figure 11 shows a 24 bpp Single-Link application using Format 1. In data Format 1, the two LSB per color are transferred on the Y3P/N LVDS lane.

Figure 12 shows a Single-Link LVDS application where 24 bpp data is received from DSI and converted to 18 bpp data for transmission to an 18 bpp panel. This application is configured by setting CHA_24BPP_FORMAT1 (CSR 0x18.1) to 1 and CHA_24BPP_MODE (CSR 0x18.3) to 0. In this configuration, the SN65DSI85-Q1 will not transmit the 2 LSB per color since the Y3P/N LVDS lane is disabled.

NOTE

Note: Figure 9, Figure 10, Figure 11, and Figure 12 only illustrate a few example applications for the SN65DSI85-Q1. Other applications are also supported.

DE = Data Enable; Channel B Clock, Channel B Data, and A_Y3P/N are Output Low

Figure 9. LVDS Output Data
Single-Link 18 bpp

DE = Data Enable; (o) = Odd Pixels; (e) = Even Pixels

Figure 10. LVDS Output Data (Format 2)
Dual-Link 24 bpp

DE = Data Enable; Channel B Clock and Data are Output Low

Figure 11. LVDS Output Data (Format 1)
Single-Link 24 bpp

DE = Data Enable; Channel B Clock, Channel B Data, and A_Y3P/N are Output Low; Channel B Clock, Channel B Data, and A_Y3P/N are Output Low

Figure 12. LVDS Output Data (Format 1)
24 bpp to Single-Link 18 bpp Conversion