ZHCSFS6B July 2016 – June 2018 SN65DSI85-Q1
PRODUCTION DATA.
Address 0x2B is shown in Figure 42 and described in Table 31.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reserved | CHB_SYNC_DELAY_HIGH | ||||||
| R/W-0 | |||||||
| LEGEND: R/W = Read/Write; R = Read only; W = Write only (reads return undetermined values); R/W1C = Read and Write 1 to Clear |
| BIT | FIELD | TYPE | RESET | DESCRIPTION |
|---|---|---|---|---|
| 7–4 | Reserved | Reserved | ||
| 3-0 | CHB_SYNC_DELAY_HIGH | R/W | 0 | This field controls the delay in pixel clocks from when an HSync or VSync is received on the DSI to when it is transmitted on the LVDS interface for Channel B when the SN65DSI85-Q1 is configured as two single stream mode with CSR 0x18.4 = 0 and CSR 0x10.6:5 = 10.
The delay specified by this field is in addition to the pipeline and synchronization delays in the SN65DSI85-Q1. The additional delay is approximately 10 pixel clocks. The Sync delay must be programmed to at least 32 pixel clocks to ensure proper operation. The value in this field is the upper 4 bits of the 12-bit value for the Sync delay. |