ZHCSFS6B July 2016 – June 2018 SN65DSI85-Q1
PRODUCTION DATA.
Address 0x22 is shown in Figure 33 and described in Table 22.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CHB_ACTIVE_LINE_LENGTH_LOW | |||||||
| R/W-0 | |||||||
| LEGEND: R/W = Read/Write; R = Read only; W = Write only (reads return undetermined values); R/W1C = Read and Write 1 to Clear |
| BIT | FIELD | TYPE | RESET | DESCRIPTION |
|---|---|---|---|---|
| 7-0 | CHB_ACTIVE_LINE_LENGTH_LOW | R/W | 0 | When the SN65DSI85-Q1 is configured for a single DSI input, this field is not applicable.
When configured for Dual DSI inputs in Odd/Even mode, this field controls the number of even pixels in the active horizontal line that are received on DSI Channel B. When configured for Dual DSI inputs in Left/Right mode, this field controls the number of right pixels in the active horizontal line that are received on DSI Channel B and output to LVDS Channel B. When configured for Dual DSI inputs in two stream mode, this field controls the number of pixels in the active horizontal line for the video stream received on DSI Channel B and output to LVDS Channel B. The value in this field is the lower 8 bits of the 12-bit value for the horizontal line length. Note: When the SN65DSI85-Q1 is configured for dual DSI inputs in Left/Right mode and RIGHT_CROP field is programmed to a value other than 0x00, the CHB_ACTIVE_LINE_LENGTH_LOW/HIGH registers must be programmed to the number of active pixels in the Right portion of the line after RIGHT_CROP has been applied. |