ZHCSFS6B July 2016 – June 2018 SN65DSI85-Q1
PRODUCTION DATA.
Address 0xE1 is shown in Figure 63 and described in Table 52.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CHA_SYNCH_ERR_EN | CHA_CRC_ERR_EN | CHA_UNC_ECC_ERR_EN | CHA_COR_ECC_ERR_EN | CHA_LLP_ERR_EN | CHA_SOT_BIT_ERR_EN | Reserved | PLL_UNLOCK_EN |
| R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
| LEGEND: R/W = Read/Write; R = Read only; W = Write only (reads return undetermined values); R/W1C = Read and Write 1 to Clear |
| BIT | FIELD | TYPE | RESET | DESCRIPTION |
|---|---|---|---|---|
| 7 | CHA_SYNCH_ERR_EN | R/W | 0 |
0: CHA_SYNCH_ERR is masked 1: CHA_SYNCH_ERR is enabled to generate IRQ events |
| 6 | CHA_CRC_ERR_EN | R/W | 0 |
0: CHA_CRC_ERR is masked 1: CHA_CRC_ERR is enabled to generate IRQ events |
| 5 | CHA_UNC_ECC_ERR_EN | R/W | 0 |
0: CHA_UNC_ECC_ERR is masked 1: CHA_UNC_ECC_ERR is enabled to generate IRQ events |
| 4 | CHA_COR_ECC_ERR_EN | R/W | 0 |
0: CHA_COR_ECC_ERR is masked 1: CHA_COR_ECC_ERR is enabled to generate IRQ events |
| 3 | CHA_LLP_ERR_EN | R/W | 0 |
0: CHA_LLP_ERR is masked 1: CHA_ LLP_ERR is enabled to generate IRQ events |
| 2 | CHA_SOT_BIT_ERR_EN | R/W | 0 |
0: CHA_SOT_BIT_ERR is masked 1: CHA_SOT_BIT_ERR is enabled to generate IRQ events |
| 1 | Reserved | Reserved | ||
| 0 | PLL_UNLOCK_EN | R/W | 0 |
0: PLL_UNLOCK is masked 1: PLL_UNLOCK is enabled to generate IRQ events |