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ZHCSFS6B July 2016 – June 2018 SN65DSI85-Q1

PRODUCTION DATA.

封裝選項(xiàng)

機(jī)械數(shù)據(jù) (封裝 | 引腳)

PAP|64
- MPQF071C

散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)

PAP|64
- PPTD318A

訂購(gòu)信息

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP⁽¹⁾	MAX	UNIT
V_IL	Low-level control signal input voltage				0.3 × V_CC	V
V_IH	High-level control signal input voltage		0.7 × V_CC			V
V_OH	High-level output voltage	I_OH = –4 mA	1.25			V
V_OL	Low-level output voltage	I_OL = 4 mA			0.4	V
I_LKG	Input failsafe leakage current	V_CC= 0; V_CC(PIN) = 1.8 V			±30	μA
I_IH	High level input current	Any input terminal			±30	μA
I_IL	Low level input current	Any input terminal			±30	μA
I_OZ	High-impedance output current	CMOS output terminals			±10	μA
I_OS	Short-circuit output current	Any output driving GND short			±50	mA
I_CC	Device active current	See ⁽²⁾		127	232	mA
I_ULPS	Device standby current	All data and clock lanes are in ultra-low power state (ULPS)		7.7	14	mA
I_RST	Shutdown current	EN = 0		0.04	130	µA
R_EN	EN control input resistor			200		kΩ
MIPI DSI INTERFACE
V_IH-LP	LP receiver input high threshold	See Figure 2	880			mV
V_IL-LP	LP receiver input low threshold	See Figure 2			550	mV
\|V_ID\|	HS differential input voltage		100		270	mV
\|V_IDT\|	HS differential input voltage threshold				50	mV
V_IL-ULPS	LP receiver input low threshold; ultra-low power state (ULPS)				300	mV
V_CM-HS	HS common mode voltage; steady-state		70		330	mV
ΔV_CM-HS	HS common mode peak-to-peak variation including symbol delta and interference				100	mV
V_IH-HS	HS single-ended input high voltage	See Figure 2			460	mV
V_IL-HS	HS single-ended input low voltage	See Figure 2	–40			mV
V_TERM-EN	HS termination enable; single-ended input voltage (both Dp AND Dn apply to enable)	Termination is switched simultaneous for Dn and Dp			450	mV
R_DIFF-HS	HS mode differential input impedance		80		125	Ω
LVDS OUTPUT
\|V_OD\|	Steady-state differential output voltage for A_Yx P/N and B_Yx P/N	CSR 0x19.3:2=00 and, or CSR 0x19.1:0=00 100 Ω near end termination	180	245	330	mV
		CSR 0x19.3:2=01 and, or CSR 0x19.1:0=01 100 Ω near end termination	215	293	392
		CSR 0x19.3:2=10 and, or CSR 0x19.1:0=10 100 Ω near end termination	250	341	455
		CSR 0x19.3:2=11 and, or CSR 0x19.1:0=11 100 Ω near end termination	290	389	515
		CSR 0x19.3:2=00 and, or CSR 0x19.1:0=00 200 Ω near end termination	150	204	275
		CSR 0x19.3:2=01 and, or CSR 0x19.1:0=01 200 Ω near end termination	200	271	365
		CSR 0x19.3:2=10 and, or CSR 0x19.1:0=10 200 Ω near end termination	250	337	450
		CSR 0x19.3:2=11 and, or CSR 0x19.1:0=11 200 Ω near end termination	300	402	535
\|V_OD\|	Steady-state differential output voltage for A_CLKP/N and B_CLKP/N	CSR 0x19.3:2=00 and, or CSR 0x19.1:0=00 100 Ω near end termination	140	191	262	mV
		CSR 0x19.3:2=01 and, or CSR 0x19.1:0=01 100 Ω near end termination	168	229	315
		CSR 0x19.3:2=10 and, or CSR 0x19.1:0=10 100 Ω near end termination	195	266	365
		CSR 0x19.3:2=11 and, or CSR 0x19.1:0=11 100 Ω near end termination	226	303	415
		CSR 0x19.3:2=00 and, or CSR 0x19.1:0=00 200 Ω near end termination	117	159	220
		CSR 0x19.3:2=01 and, or CSR 0x19.1:0=01 200 Ω near end termination	156	211	295
		CSR 0x19.3:2=10 and, or CSR 0x19.1:0=10 200 Ω near end termination	195	263	362
		CSR 0x19.3:2=11 and, or CSR 0x19.1:0=11 200 Ω near end termination	234	314	435
Δ\|V_OD\|	Change in steady-state differential output voltage between opposite binary states	RL = 100 Ω			35	mV
V_OC(SS)	Steady state common-mode output voltage⁽³⁾	CSR 0x19.6 = 1 and CSR 0x1B.6 = 1; and, or CSR 0x19.4 = 1 and CSR 0x1B.4 = 1; see Figure 3	0.75	0.9	1.13	V
V_OC(SS)	Steady state common-mode output voltage⁽³⁾	CSR 0x19.6 = 0 and, or CSR 0x19.4 = 0; see Figure 3	1	1.25	1.5	V
V_OC(PP)	Peak-to-peak common-mode output voltage	see Figure 3			35	mV
R_{LVDS_DIS}	Pulldown resistance for disabled LVDS outputs			1		kΩ

(1) All typical values are at V_CC = 1.8V and T_A = 25°C

(2) SN65DSI85-Q1: DUAL Channel DSI to DUAL Channel LVDS, 1920 x 1200

number of LVDS lanes = 2 × (3 data lanes + 1 CLK lane)
number of DSI lanes = 2 × (4 data lanes + 1 CLK lane
LVDS CLK OUT = 81.6 M
DSI CLK = 490 M
RGB888, LVDS18bpp

Maximum values are at V_CC = 1.95 V and T_A = 105°C

(3) Tested at V_CC = 1.8V , T_A = –40°C for MIN, T_A = 25°C for TYP, T_A = 105°C for MAX.