ZHCSID0D April 2016 – June 2018 LMH1226
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 4-Level Input Configuration Pins
- 7.3.2 Input Carrier Detect
- 7.3.3 Continuous Time Linear Equalizer (CTLE)
- 7.3.4 Input-Output Mux Selection
- 7.3.5 Clock and Data Recovery (CDR) Reclocker
- 7.3.6 Internal Eye Opening Monitor (EOM)
- 7.3.7 Output Function Control
- 7.3.8 Output Driver Amplitude and De-Emphasis Control
- 7.3.9 Status Indicators and Interrupts
- 7.4 Device Functional Modes
- 7.5 LMH1226 Register Map
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機械、封裝和可訂購信息
5 Pin Configuration and Functions
RTW Package
24-Pin QFN
Top View
Pin Functions
| PIN | I/O (1) | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| High-Speed Differential I/Os | |||
| IN1+ | 4 | I, Analog | Differential complementary inputs with internal 100-Ω termination. Requires external 4.7-µF AC coupling capacitors for SMPTE and 10 GbE. |
| IN1- | 5 | I, Analog | |
| OUT0+ | 18 | O, Analog | Differential complementary outputs with 100-Ω internal termination. Requires external 4.7-µF AC coupling capacitors. Output driver OUT0± can be disabled under user control. |
| OUT0- | 17 | O, Analog | |
| OUT1+ | 15 | O, Analog | Differential complementary outputs with 100 Ω internal termination. Requires external 4.7-µF AC coupling capacitors. Output driver OUT1± can be disabled under user control. |
| OUT1- | 14 | O, Analog | |
| RSV1 | 1 | Reserved pins.
Do not connect. |
|
| RSV2 | 2 | ||
| Control Pins | |||
| LOCK_N | 12 | O, LVCMOS, OD | LOCK_N is the reclocker lock indicator for the selected input. LOCK_N is pulled LOW when the reclocker has acquired locking condition. LOCK_N is an open drain output, 3.3 V tolerant, and requires an external 2-kΩ to 5-kΩ pull-up resistor to logic supply. LOCK_N pin can be re-configured to indicate INT_N (Interrupt) through register programming. |
| IN_OUT_SEL | 8 | I, 4-LEVEL | IN_OUT_SEL selects the signal flow at input ports to output ports. See Table 2 for details. This pin setting can be overridden by register control. |
| OUT_CTRL | 19 | I, 4-LEVEL | OUT_CTRL selects the signal flow from IN1± to OUT1± and OUT0±. It selects reclocked data, reclocked data and clock, bypassed reclocker data (equalized data to output driver), or bypassed equalizer and reclocker data. See Table 4 for details. This pin setting can be overridden by register control. |
| VOD_DE | 11 | I, 4-LEVEL | VOD_DE selects the driver output amplitude and de-emphasis level for both OUT0± and OUT1±. See Table 5for details. This pin setting can be overridden by register control. |
| MODE_SEL | 6 | I, 4-LEVEL | MODE_SEL enables SPI or SMBus serial control interface. See Table 6 for details. |
| Serial Control Interface (SPI Mode), MODE_SEL = F (Float) | |||
| SS_N | 7 | I, LVCMOS | SS_N is the Slave Select. When SS_N is at logic Low, it enables SPI access to the LMH1226 slave device. SS_N is a LVCMOS input reference to VDDIO. |
| MISO | 20 | O, LVCMOS | MISO is the SPI control serial data output from the LMH1226 slave device. MISO is a LVCMOS output reference to VDDIO. |
| MOSI | 10 | I, LVCMOS | MOSI is used as the SPI control serial data input to the LMH1226 slave device. MOSI is LVCMOS input reference to VDDIO. |
| SCK | 21 | I, LVCMOS | SCK is the SPI serial input clock to the LMH1226 slave device. SCK is LVCMOS reference to VDDIO. |
| Serial Control Interface (SMBus Mode) , MODE_SEL = L (1 kΩ to VSS) | |||
| ADDR0 | 7 | Strap, 4-LEVEL | ADDR[1:0] are SMBus address straps to select one of the 16 supported SMBus addresses. ADDR[1:0] are 4-level straps and are read into the device at power up. |
| ADDR1 | 20 | Strap, 4-LEVEL | |
| SDA | 10 | IO, LVCMOS, OD | SDA is the SMBus bi-directional open drain SDA data line to or from the LMH1226 slave device. SDA is an open drain IO and tolerant to 3.3 V. SDA requires an external 2-kΩ to 5-kΩ pull-up resistor to the SMBus termination voltage. |
| SCL | 21 | I, LVCMOS, OD | SCL is the SMBus input clock to the LMH1226 slave device. It is driven by a LVCMOS open drain driver from the SMBus master. SCL is tolerant to 3.3 V and requires an external 2-kΩ to 5-kΩ pull up resistor to the SMBus termination voltage. |
| Power | |||
| VSS | 3, 9, 16 | I, Ground | Ground reference. |
| VIN | 24 | I, Power | VIN is connected to an external power supply. It accepts either 2.5 V ± 5% or 1.8 V ± 5%. When VIN is powered from 2.5 V, VDD_LDO is the output of an on-chip LDO regulator. For lower power operation, both VIN and VDD_LDO should be connected to a 1.8 V supply. |
| VDDIO | 22 | I, Power | VDDIO powers the LVCMOS IO and 4-level input logic and connects to 2.5 V ± 5% supply. |
| VDD_LDO | 23 | IO, Power | VDD_LDO is the output of the internal 1.8 V LDO regulator when VIN is connected to a 2.5 V supply. VDD_LDO output requires external 1-μF and 0.1-μF bypass capacitors to VSS. The internal LDO is designed to power internal circuitry only. VDD_LDO is an input when VIN is powered from 1.8 V for lower power operation. When VIN is connected to a 1.8 V supply, both VIN and VDD_LDO should be connected to a 1.8 V supply. |
| VDD_CDR | 13 | I, Power | VDD_CDR powers the reclocker circuitry and connects to 2.5 V ± 5% supply. |
| EP | I, Ground | EP is the exposed pad at the bottom of the QFN package. The exposed pad must be connected to the ground plane through a via array. See Figure 29 for details. | |
(1) I = Input, O = Output, IO = Input or Output, OD = Open Drain, LVCMOS = 2-State Logic, 4-LEVEL = 4-State Logic