ZHCSID0D April 2016 – June 2018 LMH1226
PRODUCTION DATA.
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 4-Level Input Configuration Pins
- 7.3.2 Input Carrier Detect
- 7.3.3 Continuous Time Linear Equalizer (CTLE)
- 7.3.4 Input-Output Mux Selection
- 7.3.5 Clock and Data Recovery (CDR) Reclocker
- 7.3.6 Internal Eye Opening Monitor (EOM)
- 7.3.7 Output Function Control
- 7.3.8 Output Driver Amplitude and De-Emphasis Control
- 7.3.9 Status Indicators and Interrupts
- 7.4 Device Functional Modes
- 7.5 LMH1226 Register Map
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機械、封裝和可訂購信息
封裝選項
機械數(shù)據(jù) (封裝 | 引腳)
- RTW|24
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
- RTW|24
訂購信息
7.4.1.1 SMBus Read and Write Transactions
SMBus is a two-wire serial interface through which various system component chips can communicate with the master. Slave devices are identified by having a unique device address. The two-wire serial interface consists of SCL and SDA signals. SCL is a clock output from the master to all of the slave devices on the bus. SDA is a bidirectional data signal between the master and slave devices. The LMH1226 SMBus SCL and SDA signals are open drain and require external pull-up resistors.
Start and Stop:
The master generates start and stop patterns at the beginning and end of each transaction.
- Start: High to low transition (falling edge) of SDA while SCL is high.
- Stop: Low to high transition (rising edge) of SDA while SCL is high.
Figure 14. Start and Stop Conditions The master generates nine clock pulses for each byte transfer. The 9th clock pulse constitutes the ACK cycle. The transmitter releases SDA to allow the receiver to send the ACK signal. An ACK is recorded when the device pulls SDA low, while a NACK is recorded if the line remains high.
Figure 15. Acknowledge (ACK)