ZHCSID0D April 2016 – June 2018 LMH1226
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 4-Level Input Configuration Pins
- 7.3.2 Input Carrier Detect
- 7.3.3 Continuous Time Linear Equalizer (CTLE)
- 7.3.4 Input-Output Mux Selection
- 7.3.5 Clock and Data Recovery (CDR) Reclocker
- 7.3.6 Internal Eye Opening Monitor (EOM)
- 7.3.7 Output Function Control
- 7.3.8 Output Driver Amplitude and De-Emphasis Control
- 7.3.9 Status Indicators and Interrupts
- 7.4 Device Functional Modes
- 7.5 LMH1226 Register Map
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機械、封裝和可訂購信息
7.4.1.1.2 SMBus Read Operation Format
Reading data from a slave device consists of four parts, as illustrated in Figure 17:
- The master begins with a start condition, followed by the slave device address with the R/W bit set to 0'b.
- After an ACK from the slave device, the 8-bit register word address is written.
- After an ACK from the slave device, the master initiates a re-start condition, followed by the slave address with the R/W bit set to 1'b.
- After an ACK from the slave device, the 8-bit data is read back. The last ACK is high if there are no more bytes to read, and the last read is followed by a stop condition.
Figure 17. SMBus Read Operation