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ZHCSID0D April 2016 – June 2018 LMH1226

PRODUCTION DATA.

封裝選項(xiàng)

機(jī)械數(shù)據(jù) (封裝 | 引腳)

RTW|24
- MPQF167C

散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)

RTW|24
- QFND450A

訂購(gòu)信息

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
POWER
PD_DUAL	Power Dissipation, Dual Supply Mode	Measured with PRBS-10, Locked to 11.88 Gbps, only OUT1 enabled		214		mW
PD_{Z_DUAL}	Power Dissipation, Dual Supply Mode	Power Save Mode, no input signal		16		mW
PD_SINGLE	Power Dissipation, Single Supply Mode	Measured with PRBS-10, Locked to 11.88 Gbps, only OUT1 enabled		227		mW
PD_{Z_SINGLE}	Power Dissipation, Single Supply Mode	Power Save Mode, no input signal		27		mW
IDD_DUAL	Current Consumption, Dual Supply Mode	Measured at 2.5 V supply with PRBS-10, Locked to 11.88 Gbps, VOD = Default, only OUT1 enabled		73	80	mA
IDD_DUAL	Current Consumption, Dual Supply Mode	Measured at 1.8 V supply with PRBS-10, Locked to 11.88 Gbps, VOD = Default, only OUT1 enabled		17	25	mA
IDD_{Z_DUAL}	Current Consumption, Dual Supply Mode	Forced Power Save Mode, MODE_SEL = LEVEL-H, measured at 2.5 V supply		4	5	mA
IDD_{Z_DUAL}	Current Consumption, Dual Supply Mode	Forced Power Save Mode, MODE_SEL = LEVEL-H, measured at 1.8 V supply		3	9	mA
IDD_{TRANS_DUAL}	Current Consumption, Dual Supply Mode, Acquiring Lock, HEO/VEO Lock Monitor Disabled	Measured at 2.5 V supply with PRBS-10, Acquiring Lock, VOD = Default, OUT0 and OUT1 enabled		90	101	mA
IDD_{TRANS_DUAL}		Measured at 1.8 V supply with PRBS-10, Acquiring Lock, VOD = Default, OUT0 and OUT1 enabled		30	37	mA
VDD_LDO	LDO 1.8 V Output Voltage	VIN = 2.5 V, Single Supply Mode	1.71	1.8	1.89	V
LVCMOS DC SPECIFICATIONS
V_IH	High Level Input Voltage	2-Level Input (SS_N, SCK, MOSI), VDDIO = 2.5 V	0.7 x VDDIO		VDDIO + 0.3	V
V_IH	High Level Input Voltage	2-Level Input (SCL, SDA), VDDIO = 2.5 V	0.7 x VDDIO		3.6	V
V_IL	Low Level Input Voltage	2-Level Input (SS_N, SCK, MOSI), VDDIO = 2.5 V	-0.3		0.3 x VDDIO	V
V_IL	Low Level Input Voltage	2-Level Input (SCL, SDA), VDDIO = 2.5 V	0		0.3 x VDDIO	V
V_OH	High Level Output Voltage	IOH = -2 mA, (MISO), VDDIO = 2.5 V	0.8 x VDDIO		VDDIO	V
V_OL	Low Level Output Voltage	IOL = 2 mA, (MISO), VDDIO = 2.5 V	0		0.2 x VDDIO	V
V_OL	Low Level Output Voltage	IOL = 3 mA, (LOCK_N, SCL, SDA), VDDIO = 2.5 V	0		0.4	V
I_IH	Input High Leakage Current	SPI Mode: LVCMOS (SS_N, SCK, MOSI), Vinput = VDDIO			15	µA
I_IH	Input High Leakage Current	SMBus Mode: LVCMOS (LOCK_N, SCL, SDA), Vinput = VDDIO			10	µA
I_IL	Input Low Leakage Current	SPI: LVCMOS (SS_N), Vinput = VSS	-40			µA
		SPI: LVCMOS (SCK, MOSI), Vinput = VSS	-15
		SMBus: LVCMOS (CD_N, SCL, SDA), Vinput = VSS	-10
4-LEVEL LOGIC DC SPECIFICATIONS (REFERENCE TO VDDIO, APPLY TO ALL 4-LEVEL INPUT CONTROL PINS)
V_{4_LVL_H}	LEVEL-H Input Voltage	Pull-up 1 kΩ to VDDIO		VDDIO		V
V_{4_LVL_F}	LEVEL-F Default Voltage	Float, VDDIO = 2.5 V		2/3 x VDDIO		V
V_{4_LVL_R}	LEVEL-R Input Voltage	External Pull-down 20 kΩ to VSS, VDDIO = 2.5 V		1/3 x VDDIO		V
V_{4_LVL_L}	LEVEL-L Input Voltage	External Pull-down 1 kΩ to VSS		0		V
I_{4_LVL_IH}	Input High Leakage Current	4-Levels (IN_OUT_SEL, OUT_CTRL, VOD_DE, MODE_SEL); Vinput = VDDIO	20	45	80	µA
I_{4_LVL_IH}	Input High Leakage Current	SMBus Mode: 4-Levels (ADDR0, ADDR1), Vinput = VDDIO	20	45	80	µA
I_{4_LVL_IL}	Input Low Leakage Current	4-Levels (IN_OUT_SEL, OUT_CTRL, VOD_DE, MODE_SEL), Vinput = VSS	-160	-93	-40	µA
I_{4_LVL_IL}	Input Low Leakage Current	SMBus Mode: 4-Levels (ADDR0, ADDR1), Vinput = VSS	-160	-93	-40	µA
RECEIVER SPECIFICATIONS (IN1±)
R_{IN1_TERM}	DC Input Differential Termination	Measured across IN1+ to IN1-	80	100	120	Ω
RL_{IN1_SDD11}	Input Differential Return Loss ⁽¹⁾	SDD11, 10 MHz - 2.8 GHz		-21		dB
		SDD11, 2.8 GHz - 6 GHz		-17
		SDD11, 6 GHz - 11.1 GHz		-8
RL_{IN1_SCD11}	Differential to common mode Conversion ⁽¹⁾	SCD11, 10 MHz to 11.1 GHz		-23		dB
V_{IN1_CM_TOL}	Input AC Common Mode Voltage Tolerance			15		mV (rms)
V_{IN1_CM}	DC Common Mode Voltage	Input common mode voltage at IN1+ or IN1- to VSS		2.06		V
CD_{ON_IN1}	CD_N = LOW, Signal Detect (default), Assert ON Threshold Level	10.3125 Gbps, 1010 Clock Pattern		39		mVp-p
		10.3125 Gbps, PRBS-31 Pattern		25
		11.88 Gbps, EQ and PLL Pathological Pattern		20
CD_{OFF_IN1}	CD_N = HIGH, Signal Detect (default), De-assert OFF Threshold Level for	10.3125 Gbps, 1010 Clock Pattern		15		mVp-p
		10.3125 Gbps, PRBS-31 Pattern		15
		11.88 Gbps, EQ and PLL Pathological Pattern		18
TRANSMITTER OUTPUT (OUT0± AND OUT1±)
V_OD	Output Differential Voltage⁽⁵⁾	8T pattern, VOD_DE = LEVEL-H, see Figure 13 SD, HD, 3G, 6G, 12G, and 10 GbE		410		mVp-p
		8T pattern, VOD_DE = LEVEL-F, see Figure 13 SD, HD, 3G, 6G, 12G, and 10 GbE	485	560	620
		8T pattern, VOD_DE = LEVEL-R, see Figure 13 SD, HD, 3G, 6G, 12G, and 10 GbE		635
		8T pattern, VOD_DE = LEVEL-L, see Figure 13 SD, HD, 3G, 6G, 12G, and 10 GbE		810
VOD_DE	De-emphasized Output Differential Voltage⁽⁵⁾	8T pattern, VOD_DE = LEVEL-H, see Figure 13 SD, HD, 3G, 6G, 12G, and 10 GbE		410		mVp-p
		8T pattern, VOD_DE = LEVEL-F, see Figure 13 SD, HD, 3G, 6G, 12G, and 10 GbE		500
		8T pattern, VOD_DE = LEVEL-R, see Figure 13 SD, HD, 3G, 6G, 12G, and 10 GbE		480
		8T pattern, VOD_DE = LEVEL-L, see Figure 13 SD, HD, 3G, 6G, 12G, and 10 GbE		480
R_{OUT_TERM}	DC Output Differential Termination	Measured across OUTn+ and OUTn-	80	100	120	Ω
t_R/t_F	Output Rise/Fall Time⁽¹⁾	20% - 80% using 8T Pattern SMPTE SD, HD, 3G, 6G, 12G, and 10 GbE, measured after 1 inch trace		45		ps
RL_TX-SDD22	Output Differential Return Loss, Measured with the device powered up and outputs a 10 MHz clock signal.⁽¹⁾	SDD22, 10 MHz - 2.8 GHz		-17		dB
		SDD22, 2.8 GHz - 6 GHz		-15
		SDD22, 6 GHz - 11.1 GHz		-15
RL_TX-SCC22	Output Common Mode Return Loss, measured with the device powered up and outputs a 10 MHz clock signal.⁽²⁾	SCC22, 10 MHz - 4.75 GHz		-12		dB
RL_TX-SCC22		SCC22, 4.75 GHz - 11.1 GHz		-12		dB
V_{TX_CM}	AC Common Mode Voltage⁽²⁾	Default Setting, PRBS-31, 10.3125 Gbps		5		mV (rms)
OUTPUT JITTER
T_J	Total Jitter (BER≤1e-12), Reclocked Output⁽⁴⁾	11.88 Gbps, PRBS-10, 500 mVp-p and 1000 mVp-p launch amplitude, 20 inch FR4 board trace at IN1±		0.11	0.15	UI
		5.94 Gbps, PRBS-10, 500 mVp-p and 1000 mVp-p launch amplitude, 20 inch FR4 board trace at IN1±		0.106		UI
		2.97 Gbps, PRBS-10, 500 mVp-p and 1000 mVp-p launch amplitude, 20 inch FR4 board trace at IN1±		0.075		UI
		1.485 Gbps, PRBS-10, 500 mVp-p and 1000 mVp-p launch amplitude, 20 inch FR4 board trace at IN1±		0.07		UI
		270 Mbps, PRBS-10, 500 mVp-p and 1000 mVp-p launch amplitude, 20 inch FR4 board trace at IN1±		0.07		UI
		10.3125 Gbps, PRBS-10, 500 mVp-p and 1000 mVp-p launch amplitude, 20 inch FR4 board trace at IN1±		0.09	0.15	UI
R_J	Random Jitter, Reclocked Output	11.88 Gbps, PRBS-10, 500 mVp-p and 1000 mVp-p launch amplitude, 20 inch FR4 board trace at IN1±		5		mUI (rms)
R_J	Random Jitter, Reclocked Output	10.3125 Gbps, PRBS-10, 500 mVp-p and 1000 mVp-p launch amplitude, 20 inch FR4 board trace at IN1±		4.1		mUI (rms)
D_J	Deterministic Jitter, Reclocked Output	11.88 Gbps, PRBS-10, 500 mVp-p and 1000 mVp-p launch amplitude, 20 inch FR4 board trace at IN1±		40		mUI
D_J	Deterministic Jitter, Reclocked Output	10.3125 Gbps, PRBS-10, 500 mVp-p and 1000 mVp-p launch amplitude, 20 inch FR4 board trace at IN1±		34		mUI
TJ_RAW	Total Jitter (BER≤1e-12), RAW (Reclocker Bypassed)	125 Mbps, PRBS-10, 500 mVp-p and 1000 mVp-p launch amplitude, 20 inch FR4 board trace at IN1±		0.17		UI
TJ_RAW	Total Jitter (BER≤1e-12), RAW (Reclocker Bypassed)	1.25 Gbps, PRBS-10, 500 mVp-p and 1000 mVp-p launch amplitude, 20 inch FR4 board trace at IN1±		0.17		UI
CLOCK AND DATA RECOVERY
LOCK_RATE	Reclocker Lock Data Rates	SMPTE 12G, /1		11.88		Gbps
		SMPTE 12G, /1.001		11.868		Gbps
		SMPTE 6G, /1		5.94		Gbps
		SMPTE 6G, /1.001		5.934		Gbps
		SMPTE 3G, /1		2.97		Gbps
		SMPTE 3G, /1.001		2.967		Gbps
		SMPTE HD, /1		1.485		Gbps
		SMPTE HD, /1.001		1.4835		Gbps
		SMPTE SD, /1		270		Mbps
		10 GbE		10.3125		Gbps
BYPASS_RATE	Bypass reclocker data rate	MADI		125		Mbps
BYPASS_RATE	Bypass reclocker data rate	1 GbE		1.25		Gbps
BW_PLL	PLL Bandwidth	Measured with 0.2 UI SJ at -3 dB, 10.3125 Gbps		8		MHz
		Measured with 0.2 UI SJ at -3 dB, 11.88 Gbps		13
		Measured with 0.2 UI SJ at -3 dB, 5.94 Gbps		7
		Measured with 0.2 UI SJ at -3 dB, 2.97 Gbps		5
		Measured with 0.2 UI SJ at -3 dB, 1.485 Gbps		3
		Measured with 0.2 UI SJ at -3 dB, 270 Mbps		1
J_PEAKING	PLL Jitter Peaking	SD, HD, 3G, 6G, 12G, and 10 GbE		0.3		dB
J_{TOL_IN1}	IN1 Input Jitter Tolerance per SFF-8431 Appendix D.11	Total jitter tolerance combination of Dj, Pj, and Rj at 10 GbE, with RX stress eye mask Y1, Y2 limits		>0.7		UI
J_TOL	IN1 Input Jitter Tolerance with SJ	Sinusoidal jitter, tested at 3G, 6G and 12G; SJ amplitude low to high sweep, tested at BER ≤ 1e-12		0.65		UI
T_LOCK	Reclocker lock time	All supported data rates, disable HEO/VEO monitor		5		ms
TEMP_LOCK	VCO Lock with Temp Ramp	Lock Temperature Range (5 °C per min, ramp up and down), -40°C to 85°C operating range		125		°C
T_LATENCY	Reclocker Latency⁽³⁾	IN1, all supported data rates		1.5 UI + 190		ps
T_PD-RAW	Propagation Delay	Raw Data (reclocker bypassed), IN1± EQ = default		190		ps
FCLK_OUT	Output Clock Frequency OUT1 Programmed to Output Recovered Clock	Operating at 11.88 Gbps		297		MHz
		Operating at 5.94 Gbps		297		MHz
		Operating at 2.97 Gbps		2.97		GHz
		Operating at 1.485 Gbps		1.485		GHz
		Operating at 270 Mbps		270		MHz

(1) This parameter was measured with an LMH1219EVM.

(2) This parameter was measured with an LMH1219EVM.

(3) This parameter is data rate dependent. For example, at 11.88 Gbps, 1.5 UI = 1.5 x 84.17 ps = 126.25 ps. Therefore, T_Latency = (126.25 + 190) ps = 316.25 ps.

(4) These limits are ensured by bench characterization and are not production tested.

(5) ATE production tested with DC method.