ZHCSID0D April 2016 – June 2018 LMH1226
PRODUCTION DATA.
- 1 特性
- 2 應(yīng)用
- 3 說(shuō)明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 4-Level Input Configuration Pins
- 7.3.2 Input Carrier Detect
- 7.3.3 Continuous Time Linear Equalizer (CTLE)
- 7.3.4 Input-Output Mux Selection
- 7.3.5 Clock and Data Recovery (CDR) Reclocker
- 7.3.6 Internal Eye Opening Monitor (EOM)
- 7.3.7 Output Function Control
- 7.3.8 Output Driver Amplitude and De-Emphasis Control
- 7.3.9 Status Indicators and Interrupts
- 7.4 Device Functional Modes
- 7.5 LMH1226 Register Map
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機(jī)械、封裝和可訂購(gòu)信息
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RTW|24
散熱焊盤(pán)機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RTW|24
訂購(gòu)信息
8.2.4 Application Performance Plots
The LMH1226 performance was measured with the test setup shown in Figure 22.
Figure 22. Test Setup for LMH1226 PCB Equalizer (IN1±) The eye diagrams in this subsection show how the LMH1226 improves overall signal integrity in the data path for 100-Ω differential FR4 PCB trace at IN1.
A. VOD_DE = H, IN_OUT_SEL = L, OUT_CTRL = L
Figure 23. 10.3125 Gbps, TL = 20 in. 5-Mil FR4, EQ Only 
A. VOD_DE = H, IN_OUT_SEL = H, OUT_CTRL = L
Figure 25. 11.88 Gbps, TL = 20 in. 5-Mil FR4, EQ Only 
A. VOD_DE = H, IN_OUT_SEL = L, OUT_CTRL = F
Figure 24. 10.3125 Gbps, TL = 20 in. 5-Mil FR4, Reclocked 
A. VOD_DE = H, IN_OUT_SEL = H, OUT_CTRL = F
Figure 26. 11.88 Gbps, TL = 20 in. 5-Mil FR4, Reclocked