10 Revision History
Changes from Revision E (February 2024) to Revision F (December 2024)
- Updated JTAG_CLK
descriptionGo
- Added clarity to BMSR Register's MF Preamble Suppression descriptionGo
Changes from Revision D (November 2022) to Revision E (February 2024)
- Add SGMII output sectionGo
- Remove the duplicate timing diagramGo
- Edit Wake on Lan sectionGo
- Edit Magic Packet StructureGo
- Change Magic Packet ExampleGo
- Edit Wake-on-LAN Configuration and StatusGo
- Added section
Section 7.3.2.1
Go
- Edit Extended Address Space
AccessGo
- Edit Write (No Post Increment) OperationGo
- Edit Read (No Post Increment) OperationGo
- Edit Write (Post Increment) OperationGo
- Edit Read (Post Increment) OperationGo
- Clean up the languageGo
- Clarify register 0x0004 half duplex advertisement bit Go
- Updated Auto-Negotiation Advertisement Register (ANAR)
registerGo
- Edit default value for bit [1:0]Go
- Added
Section 7.6.37
register.Go
- Add register 0x00A0 contentGo
- Add register 0x00A1 contentGo
- Add register 0x00A2 contentGo
- Add register 0x00A3 contentGo
- Added
Section 7.6.54
register.Go
- Add TDR Peak Sign infoGo
- Updated the Cable Line Driver sectionGo
- Add a note on power supply recommendation sesssion Go
Changes from Revision C (October 2019) to Revision D (November 2022)
- 更新了 IEEE 1588 時間戳的幀起始檢測Go
- Updated Electrical CharacteristicsGo
- Added Phy has internal 100 Ohm differential termination in Section 7.4.1.1
Go
- Added following wording to the end of first paragraph in Section 7.4.3.9 "DP83867 devices manufactured after August, 2022, have an increased random seed value
that now includes 255 different seed values to expedite Auto-MDIX resolution with a link
partner."Go
- Changed Bit 11:10 SPEED_OPT_ATTEMPT_CNT to RW description in
Go
- Changed bits 15:9, so that bit 12 can be '1'. Bit 7 description updated
Section 7.6.31
Go
- Added Register 0x008AGo
- Added Register 0x00B3Go
- Added Register 0x00C0Go
- Added Register 0x0100Go
Changes from Revision A (February 2017) to Revision B (March 2017)
- Changed pin 6 name in the pinout diagram from: VDDA1P0 to: VDD1P0Go
- Changed
INT /
PWDN Interrupt descriptionGo
- Changed RESERVED bit number from: 15:8 to: 15:9 Go
- Changed RESERVED bit number from: 7 to: 8:7 Go
- Changed the default and description of the CLK_O_DISABLE bit (bit 6)Go
- Clarified Figure 8-2
Go
- Changed text in MDI traces bullet from: or to: andGo
Changes from Revision * (October 2015) to Revision A (February 2017)
- 根據最新文檔和翻譯標準更新了數據表文本Go
- Added storage temperature to
Section 6.1
Go
- Updated parameter symbol from VIH to VIH
Go
- Added MDC toggling clarification to
Section 6.7
Go
- Added
Section 6.11
Go
- Added DP83867IS/CS Start of Frame Detection TimingGo
- Added section
Section 7.3.2.1
Go
- Changed target strap voltage thresholds Table 7-5
Go
- Changed values for RX_CTRL pin for modes 1 and 2 to N/A in Table 7-6
Go
- Changed strap name SPEED_SEL to ANEG_SEL in Table 7-6
Go
- Changed table name Speed Select Strap Details to Auto-Negotiation Select Strap Details in Table 7-7
Go
- Changed strap option SPEED_SEL to ANEG_SEL in Table 7-7
Go
- Changed mode 5 RGMII Clock Skew value from 4.0ns to 0ns in Table 7-8
Go
- Changed strap control of Speed Select bit 13 in Table 7-10
Go
- Changed strap control of Speed Select bit 6 in Table 7-10
Go
- Changed bit 9 name from 100BASE-T FULL DUPLEX to 1000BASE-T FULL DUPLEX in Table 7-19
Go
- Changed bit 9 descriptions from half duplex to full duplex in Table 7-19
Go
- Changed 'Interrupt Status and Event Control Register (ISR)' to 'MII Interrupt Control Register (MICR)' in
Section 7.6.16
Go
- Changed Register definition to move a statement from
Section 7.6.17
to
Section 7.6.16
Go
- Changed default of bit 9 from '1' to '0' in Table 7-28
Go
- Changed default of bits 5:0 from '0' to '0 0111' in Table 7-28
Go
- Added
Section 7.6.29
registerGo
- Added
Section 7.6.37
registerGo
- Changed SPEED_SEL strap bit name to ANEG_SEL in Strap Configuration
Status Register 1 (STRAP_STS1), Address 0x006EGo
- Changed name of Bit 6:4 from 'STRAP_GMII_CLK_SKEW_TX' to 'STRAP_RGMII_CLK_SKEW_TX' in Table 7-49
Go
- Changed name of Bit 6:4 from 'STRAP_GMII_CLK_SKEW_RX' to 'STRAP_RGMII_CLK_SKEW_RX' in Table 7-49
Go
- Added Section 7.6.54 registerGo
- Changed default of bits 12:8 to 0 1100 in Table 7-114
Go
- Changed description for IO_IMPEDANCE_CTRL bits in Section 7.6.104
Go
- Changed
Section 8.3
sectionGo
- Added power down supply sequence sentence in
Section 8.3
Go
- Added Figure 8-9
Go
- Added Table 8-5
Go
- Added note regarding 1.8V supply sequence if no load exists on 2.5V supply in
Layout
Go