ZHCSEC3F October 2015 – January 2025 DP83867CS , DP83867E , DP83867IS
PRODUCTION DATA
請參考 PDF 數據表獲取器件具體的封裝圖。
| PARAMETER | TEST CONDITIONS(1) | MIN | NOM | MAX | UNIT | |
|---|---|---|---|---|---|---|
| T1 | Post power-up stabilization time prior to MDC preamble for register accesses | MDIO is pulled high for 32-bit serial management initialization. | 200 | ms | ||
| T2 | Hardware configuration latch-in time from power up | Hardware Configuration Pins are described in Section 7.5.1. | 200 | ms | ||
| T3 | Hardware configuration pins transition to output drivers | 64 | ns | |||