ZHCSEC3F October 2015 – January 2025 DP83867CS , DP83867E , DP83867IS
PRODUCTION DATA
請(qǐng)參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
| BIT | BIT NAME | DEFAULT | DESCRIPTION |
|---|---|---|---|
| 15:11 | RESERVED | 0, RO | RESERVED |
| 10 | STRAP_ FLD | Strap, RO | Fast Link Drop (FLD) Enable Strap: 1 = FLD strapped to enable. 0 = FLD strapped to disable. |
| 10 | RESERVED | 0, RO | RESERVED |
| 9 | RESERVED | 0, RO | RESERVED |
| 8 | RESERVED | 0, RO | RESERVED |
| 7 | RESERVED | 0, RO | RESERVED |
| 6:4 | STRAP_RGMII_CLK_SKEW_TX (RGZ) | Strap, RO | RGMII Transmit Clock Skew Strap: RGMII_TX_DELAY_CTRL[2:0] values from straps. See RGMII Transmit Clock Skew Details table for more information. |
| 6:4 | STRAP_RGMII_CLK_SKEW_TX | Strap, RO | RGMII Transmit Clock Skew Strap: RGMII_TX_DELAY_CTRL[2:0] values from straps. See RGMII Transmit Clock Skew Details table for more information. |
| 3 | RESERVED | 0, RO | RESERVED |
| 2:0 | STRAP_RGMII_CLK_SKEW_RX | Strap, RO | RGMII Receive Clock Skew Strap: RGMII_RX_DELAY_CTRL[2:0] values from straps. See Table 7-8 for more information. |