ZHCSEC3F October 2015 – January 2025 DP83867CS , DP83867E , DP83867IS
PRODUCTION DATA
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
| PIN | TYPE(1) | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| MAC INTERFACES (SGMII, RGMII) | |||
| TX_D3 | 25 | I, PD | TRANSMIT DATA Bit 3: This signal carries data from the MAC to the PHY in RGMII mode. This pin is synchronous to the transmit clock GTX_CLK. |
| TX_D2 | 26 | I, PD | TRANSMIT DATA Bit 2: This signal carries data from the MAC to the PHY in RGMII mode. This pin is synchronous to the transmit clock GTX_CLK. |
| SGMII_SIP | 27 | I, PD | Differential SGMII Data Input: This signal carries
data from the MAC to the PHY in SGMII mode. This pin is synchronous to the
differential SGMII clock input. This pin can be AC-coupled to the MAC through a 0.1μF capacitor when operating in SGMII mode. |
| TX_D1 | 27 | I, PD | TRANSMIT DATA Bit 1: This signal carries data from the MAC to the PHY in RGMII mode. This pin is synchronous to the transmit clock GTX_CLK. |
| SGMII_SIN | 28 | I, PD | Differential SGMII Data Input: This signal carries
data from the MAC to the PHY in SGMII mode. This pin is synchronous to the
differential SGMII clock input. This pin can be AC-coupled to the MAC through a 0.1μF capacitor when operating in SGMII mode. |
| TX_D0 | 28 | I, PD | TRANSMIT DATA Bit 0: This signal carries data from the MAC to the PHY in RGMII mode. This pin is synchronous to the transmit clock GTX_CLK. |
| GTX_CLK | 29 | I, PD | RGMII TRANSMIT CLOCK: This continuous clock signal is sourced from the MAC layer to the PHY. Nominal frequency is 125MHz. |
| RX_CLK | 32 | O | RGMII RECEIVE CLOCK: Provides the recovered receive clocks for different modes of operation: 2.5MHz in 10Mbps mode. 25MHz in 100Mbps mode. 125MHz in 1000Mbps mode. |
| SGMII_COP | 33 | S, O | Differential SGMII Clock Output: This signal is a
continuous 625MHz clock signal driven by the PHY in SGMII mode. This pin can be AC-coupled to the MAC through a 0.1μF capacitor when operating in SGMII mode. |
| RX_D0 | 33 | S, O, PD | RECEIVE DATA Bit 0: This signal carries data from the PHY to the MAC in RGMII mode. This pin is synchronous to the receive clock RX_CLK. |
| SGMII_CON | 34 | S, O, PD | Differential SGMII Clock Output: This signal is a
continuous 625MHz clock signal driven by the MAC in SGMII mode. This pin can be AC-coupled to the MAC through a 0.1μF capacitor when operating in SGMII mode. |
| RX_D1 | 34 | O, PD | RECEIVE DATA Bit 1: This signal carries data from the PHY to the MAC in RGMII mode. This pin is synchronous to the receive clock RX_CLK. |
| SGMII_SOP | 35 | S, O, PD | Differential SGMII Data Output: This signal carries data from the PHY to the MAC in SGMII mode. This pin is synchronous to the differential SGMII clock output. |
| This pin can be AC-coupled to the MAC through a 0.1μF capacitor when operating in SGMII mode. | |||
| RX_D2 | 35 | S, O, PD | RECEIVE DATA Bit 2: This signal carries data from the PHY to the MAC in RGMII mode. This pin is synchronous to the receive clock RX_CLK. |
| SGMII_SON | 36 | S, O, PD | Differential SGMII Data Output: This signal carries
data from the PHY to the MAC in SGMII mode. This pin is synchronous to the
differential SGMII clock output. This pin can be AC-coupled to the MAC through a 0.1μF capacitor when operating in SGMII mode. |
| RX_D3 | 36 | O, PD | RECEIVE DATA Bit 3: This signal carries data from the PHY to the MAC in RGMII mode. This pin is synchronous to the receive clock RX_CLK. |
| TX_CTRL | 37 | I, PD | TRANSMIT CONTROL: In RGMII mode, This pin combines the transmit enable and the transmit error signals of GMII mode using both clock edges. |
| RX_CTRL | 38 | S, O, PD | RECEIVE CONTROL: In RGMII mode, the receive data available and receive error are combined (RXDV_ER) using both rising and falling edges of the receive clock (RX_CLK). |
| GENERAL-PURPOSE I/O | |||
| GPIO_0 | 39 | S, O, PD | General-Purpose I/O: This signal provides a multi-function configurable I/O. Refer to the GPIO_MUX_CTRL register for details. |
| GPIO_1 | 40 | S, O, PD | General-Purpose I/O: This signal provides a multi-function configurable I/O. Refer to the GPIO_MUX_CTRL register for details. |
| MANAGEMENT INTERFACE | |||
| MDC | 16 | I, PD | MANAGEMENT DATA CLOCK: Synchronous clock to the MDIO serial management input and output data. This clock can be asynchronous to the MAC transmit and receive clocks. The maximum clock rate is 25MHz and no minimum. |
| MDIO | 17 | I/O | MANAGEMENT DATA I/O: Bidirectional management instruction and data signal that can be sourced by the management station or the PHY. This pin requires pullup resistor. The IEEE specified resistor value is 1.5kΩ, but a 2.2kΩ is acceptable. |
| INT / PWDN | 44 | I/O, PU | INTERRUPT / POWER DOWN: The default function of this pin is POWER DOWN. POWER DOWN: This is an Active Low Input. Asserting this signal low enables the power-down mode of operation. In this mode, the device powers down and consume minimum power. Register access is available through the Management Interface to configure and power up the device. INTERRUPT: When operating the pin as an interrupt, this pin uses an open-drain architecture. TI recommends using an external 2.2kΩ resistor connected to the VDDIO supply. |
| RESET | |||
| RESET_N | 43 | I, PU | RESET: The active low RESET initializes or reinitializes the DP83867. All internal registers re-initialize to default state upon assertion of RESET. The RESET input must be held low for a minimum of 1μs. |
| CLOCK INTERFACE | |||
| XI | 15 | I | CRYSTAL/OSCILLATOR INPUT: 25MHz oscillator or crystal input (50ppm) |
| XO | 14 | O | CRYSTAL OUTPUT: Second terminal for 25MHz crystal. Must be left floating if a clock oscillator is used. |
| CLK_OUT | 18 | O | CLOCK OUTPUT: Output clock |
| JTAG INTERFACE | |||
| JTAG_CLK | 20 | I, PU | JTAG TEST CLOCK: IEEE 1149.1 Test Clock input, primary clock source for all test logic input and output controlled by the testing entity. Supports a maximum clock frequency of 2.5MHz. |
| JTAG_TDO | 21 | O | JTAG TEST DATA OUTPUT: IEEE 1149.1 Test Data Output pin, the most recent test results are scanned out of the device through TDO. |
| JTAG_TMS | 22 | I, PU | JTAG TEST MODE SELECT: IEEE 1149.1 Test Mode Select pin, the TMS pin sequences the Tap Controller (16-state FSM) to select the desired test instruction. TI recommends applying 3 clock cycles with JTAG_TMS high to reset the JTAG. |
| JTAG_TDI | 23 | I, PU | JTAG TEST DATA INPUT: IEEE 1149.1 Test Data Input pin, test data is scanned into the device through TDI. |
| LED INTERFACE | |||
| LED_2 | 45 | S, I/O, PD | LED_2: By default, this pin indicates receive or transmit activity. Additional functionality is configurable through LEDCR1[11:8] register bits. |
| LED_1 | 46 | S, I/O, PD | LED_1: By default, this pin indicates that 1000BASE-T link is established. Additional functionality is configurable through LEDCR1[7:4] register bits. |
| LED_0 | 47 | S, I/O, PD | LED_0: By default, this pin indicates that link is established. Additional functionality is configurable through LEDCR1[3:0] register bits. |
| MEDIA DEPENDENT INTERFACE | |||
| TD_P_A | 1 | A | Differential Transmit and Receive Signals |
| TD_M_A | 2 | A | Differential Transmit and Receive Signals |
| TD_P_B | 4 | A | Differential Transmit and Receive Signals |
| TD_M_B | 5 | A | Differential Transmit and Receive Signals |
| TD_P_C | 7 | A | Differential Transmit and Receive Signals |
| TD_M_C | 8 | A | Differential Transmit and Receive Signals |
| TD_P_D | 10 | A | Differential Transmit and Receive Signals |
| TD_M_D | 11 | A | Differential Transmit and Receive Signals |
| OTHER PINS | |||
| RBIAS | 12 | A | Bias Resistor Connection. A 11kΩ ±1% resistor can be connected from RBIAS to GND. |
| POWER AND GROUND PINS | |||
| VDDA2P5 | 3, 9 | P | 2.5V Analog Supply (±5%). Each pin requires a 1μF and 0.1μF capacitor to GND. |
| VDD1P0 | 6, 24, 31, 42 | P | 1V Analog Supply (+15.5%, –5%). Each pin requires a 1μF and 0.1μF capacitor to GND. |
| VDDA1P8 | 13, 48 | P | 1.8V Analog Supply (±5%). No external supply is required for this pin. When unused, no connections can be made to this pin. For additional power savings, an external 1.8V supply can be connected to these pins. When using an external supply, each pin requires a 1μF and 0.1μF capacitor to GND. |
| VDDIO | 19, 30, 41 | P | I/O Power: 1.8V (±5%), 2.5V (±5%) or 3.3V (±5%). Each pin requires a 1μF and 0.1μF capacitor to GND |
| GND | Die Attach Pad | P | Ground |
The definitions below define the functionality of each pin.