ZHCSEC3F October 2015 – January 2025 DP83867CS , DP83867E , DP83867IS
PRODUCTION DATA
請參考 PDF 數據表獲取器件具體的封裝圖。
The DP83867 can be configured to generate an interrupt when changes of internal status occur. The interrupt allows a MAC to act upon the status in the PHY without polling the PHY registers. The interrupt source can be selected through the interrupt registers, MICR (register address 0x0012) and ISR (register address 0x0013).