This section has three register map summary tables with registers listed per the order of the register address:
- The NVM (OTP) shadow registers. These read/write-able shadow registers are
reset with OTP values programmed in the customer OTP space. To program the
custom OTP space, host writes the desired values to these OTP shadow
registers and follows the programming procedure. These registers are
included in the OTP CRC check. If customer OTP space is not programmed. The
shadow registers are loaded with factory configuration default value. If the
OTP (either factory configuration default or value programmed in customer
OTP space) is failing to load after a device reset, the shadow registers
will be loaded with the hardware reset default value instead. The hardware
reset default value and the factory configuration default values are the
same for the majority of the OTP shadow registers. Only the
DIR0_ADDR_OTP, DIR1_ADD_OTP, PWR_TRANSIT_CONF,
CUST_CRC_HI/LO registers have a reset value versus factory
default, and are specified in Section 8.5.1 and their register field descriptions.
- The Read/Write registers. These are registers that the host can read/write to during runtime. A device reset will put these registers back to their reset value.
- The Read registers. These are registers that the host only has read access. A device reset will put these registers back to their reset value.
The register summary tables use the following key:
- Addr = Register address
- Hex = Hexidecimal value
- NVM = Non-volatile memory (OTP) shadow registers
- RSVD = Reserved. Reserved register addresses or bits are not implemented in the device. Any write to these bits is ignored. Reads to these bits always return 0.
- REG_INT_RSVD = Reserved register or bits for internal device usage. Host must have write to this register, other it may interrupt normal operation. Value display in this register shall be ignored.
- OTP_SPARE: These are spare OTP and shadow register bits that are implemented in the device. These spare bits are included as part of the CRC calculation. These bits are read/write as normal, but do not perform any function or influence any device behaviors.
- OTP_RSVDn = OTP and shadowed registers that are implemented but are reserved for device internal usage, where n refers to the register address. MCU must keep these registers in their default value
- HW Reset default is the value loaded when digital resets (POR like event)
whereas Factory Configuration Default is the default value loaded into the
OTP cell if customer doesn't program it themselves. Customer cannot read the
HW Reset value.
Section 8.5.4 describes the definition of each bit in the registers. The registers in this
section are grouped per functional blocks.