ZHCSTD4B September 2019 – October 2023 BQ75614-Q1
PRODUCTION DATA
Figure 6-1 PAP Package 64-Pin HTQFP Top View| PIN | TYPE(1) | DESCRIPTION | |
|---|---|---|---|
| NAME | No. | ||
| BAT | 1 | P | Power supply input and top of module measurement input. Connect to the top cell of the battery module. |
| NPNB | 48 | P | Connect to the base of an external NPN transistor. |
| LDOIN | 47 | P | 6-V preregulated analog power supply input/sense pin. Connect to the emitter of the external NPN transistor and connect a 0.1-μF decoupling capacitor to CVSS. |
| AVDD | 38 | P | 5-V regulated output. AVDD supplies the internal analog circuits. Bypass AVDD with a capacitor to AVSS. |
| AVSS | 39 | GND | Analog ground. Ground connection for internal analog circuits. Connect DVSS, CVSS, REFHM, and AVSS externally. All ground pins must not be left unconnected. |
| NEG5V | 44 | P | Negative 5-V charge pump used for Main ADC. Connect with a capacitor to CVSS. |
| DVDD | 49 | P | 1.8-V regulated output. DVDD supplies the internal digital circuits. Bypass DVDD with a capacitor to DVSS. |
| DVSS | 50 | GND | Digital ground. Ground connection for internal digital logics. Connect DVSS, CVSS, REFHM, and AVSS externally. All ground pins must be connected to ground. |
| CVDD | 45 | P | 5-V I/Os power supply. CVDD supplies the I/O pins. This power supply also supports an additional 10-mA external load in ACTIVE and SLEEP. |
| CVSS | 46 | GND | Ground connection. Connect DVSS, CVSS, REFHM, and AVSS externally. All ground pins must be connected to ground. |
| TSREF | 51 | P | 5-V bias voltage for NTC thermistor. Connect TSREF to the top of the NTC resistor divider network to the GPIOs when they are configured for NTC temperature monitoring. Bypass TSREF with a capacitor to CVSS. |
| REFHP | 37 | P | Precision reference output pin. Bypass with a capacitor to REFHM. |
| REFHM | 36 | GND | Precision reference ground. Ground connection for the internal precision reference. Connect DVSS, CVSS, REFHM, and AVSS externally. All ground pins must be connected to ground. |
| SW2 / VC16 | 3 | I | Cell voltage sense input or fuse/relay sense input. Connect to the positive terminal of cell 16 (if cell is connected) or connect for fuse/relay sensing. Connect a differential RC filter to VC15. |
| SW1 / VC15 | 5 | I | Cell voltage sense input or fuse/relay sense input. Connect to the positive terminal of cell 15 (if cell is connected) or connect for fuse/relay sensing. Connect a differential RC filter to VC14 when this pin is used. |
| VC14 | 7 | I | Cell voltage sense input. Connect to the positive terminal of cell 14. Connect a differential RC filter to VC13. |
| VC13 | 9 | I | Cell voltage sense input. Connect to the positive terminal of cell 13. Connect a differential RC filter to VC12. |
| VC12 | 11 | I | Cell voltage sense input. Connect to the positive terminal of cell 12. Connect a differential RC filter to VC11. |
| VC11 | 13 | I | Cell voltage sense input. Connect to the positive terminal of cell 11. Connect a differential RC filter to VC10. |
| VC10 | 15 | I | Cell voltage sense input. Connect to the positive terminal of cell 10. Connect a differential RC filter to VC9. |
| VC9 | 17 | I | Cell voltage sense input. Connect to the positive terminal of cell 9. Connect a differential RC filter to VC8. |
| VC8 | 19 | I | Cell voltage sense input. Connect to the positive terminal of cell 8. Connect a differential RC filter to VC7. |
| VC7 | 21 | I | Cell voltage sense input. Connect to the positive terminal of cell 7. Connect a differential RC filter to VC6. |
| VC6 | 23 | I | Cell voltage sense input. Connect to the positive terminal of cell 6. Connect a differential RC filter to VC5. |
| VC5 | 25 | I | Cell voltage sense input. Connect to the positive terminal of cell 5. Connect a differential RC filter to VC4. |
| VC4 | 27 | I | Cell voltage sense input. Connect to the positive terminal of cell 4. Connect a differential RC filter to VC3. |
| VC3 | 29 | I | Cell voltage sense input. Connect to the positive terminal of cell 3. Connect a differential RC filter to VC2. |
| VC2 | 31 | I | Cell voltage sense input. Connect to the positive terminal of cell 2. Connect a differential RC filter to VC1. |
| VC1 | 33 | I | Cell voltage sense input. Connect to the positive terminal of cell 1. Connect a differential RC filter to VC0. |
| VC0 | 35 | I | Cell voltage sense input. Connect to the negative terminal of cell 1. Connect a differential RC filter to AVSS. |
| NC | 2 | I/O | No connection. Leave pin floating. |
| NC | 4 | I/O | No connection. Leave pin floating. |
| CB14 | 6 | I/O | Cell balance connection. This pin is connected to the internal cell balancing FET. Connect this pin to the positive terminal of cell 14 with a differential RC filter to CB13. The filter resistor also sets the internal balance current. |
| CB13 | 8 | I/O | Cell balance connection. This pin is connected to the internal cell balancing FET. Connect this pin to the positive terminal of cell 13 with a differential RC filter to CB12. The filter resistor also sets the internal balance current. |
| CB12 | 10 | I/O | Cell balance connection. This pin is connected to the internal cell balancing FET. Connect this pin to the positive terminal of cell 12 with a differential RC filter to CB11. The filter resistor also sets the internal balance current. |
| CB11 | 12 | I/O | Cell balance connection. This pin is connected to the internal cell balancing FET. Connect this pin to the positive terminal of cell 11 with a differential RC filter to CB10. The filter resistor also sets the internal balance current. |
| CB10 | 14 | I/O | Cell balance connection. This pin is connected to the internal cell balancing FET. Connect this pin to the positive terminal of cell 10 with a differential RC filter to CB9. The filter resistor also sets the internal balance current. |
| CB9 | 16 | I/O | Cell balance connection. This pin is connected to the internal cell balancing FET. Connect this pin to the positive terminal of cell 9 with a differential RC filter to CB8. The filter resistor also sets the internal balance current. |
| CB8 | 18 | I/O | Cell balance connection. This pin is connected to the internal cell balancing FET. Connect this pin to the positive terminal of cell 8 with a differential RC filter to CB7. The filter resistor also sets the internal balance current. |
| CB7 | 20 | I/O | Cell balance connection. This pin is connected to the internal cell balancing FET. Connect this pin to the positive terminal of cell 7 with a differential RC filter to CB6. The filter resistor also sets the internal balance current. |
| CB6 | 22 | I/O | Cell balance connection. This pin is connected to the internal cell balancing FET. Connect this pin to the positive terminal of cell 6 with a differential RC filter to CB5. The filter resistor also sets the internal balance current. |
| CB5 | 24 | I/O | Cell balance connection. This pin is connected to the internal cell balancing FET. Connect this pin to the positive terminal of cell 5 with a differential RC filter to CB4. The filter resistor also sets the internal balance current. |
| CB4 | 26 | I/O | Cell balance connection. This pin is connected to the internal cell balancing FET. Connect this pin to the positive terminal of cell 4 with a differential RC filter to CB3. The filter resistor also sets the internal balance current. |
| CB3 | 28 | I/O | Cell balance connection. This pin is connected to the internal cell balancing FET. Connect this pin to the positive terminal of cell 3 with a differential RC filter to CB2. The filter resistor also sets the internal balance current. |
| CB2 | 30 | I/O | Cell balance connection. This pin is connected to the internal cell balancing FET. Connect this pin to the positive terminal of cell 2 with a differential RC filter to CB1. The filter resistor also sets the internal balance current. |
| CB1 | 32 | I/O | Cell balance connection. This pin is connected to the internal cell balancing FET. Connect this pin to the positive terminal of cell 1 with a differential RC filter to CB0. The filter resistor also sets the internal balance current. |
| CB0 | 34 | I/O | Cell balance connection. This pin is connected to the internal cell balancing FET. Connect to the negative terminal of cell 1 with differential RC filter to AVSS. The filter resistor also sets the internal balance current. |
| SRP | 64 | I | Current sense resistor connection. With SRP and SRN connected to each end of a current sense resistor. |
| SRN | 63 | I | Current sense resistor connection. With SRP and SRN connected to each end of a current sense resistor. |
| RX | 52 | I | UART receiver input. Pull up to CVDD with an external resistor and connect the device RX to the TX output of the host MCU. If unused, connect RX to CVDD. |
| TX | 53 | O | UART transmitter output. Connect device TX to RX input of the host MCU and will be pulled up from the host side. If unused, leave it floating. |
| NC | 40, 41, 42, 43 | I/O | No connection. Leave pin floating. |
| NFAULT | 62 | O | Fault indication output. Active low. Pull up NFAULT to CVDD with a pullup resistor and connect NFAULT to host MCU GPIO. If unused, leave it unconnected. |
| GPIO1 | 61 | I/O | General purpose input/output, configuration options are:
|
| GPIO2 | 60 | I/O | |
| GPIO3 | 59 | I/O | |
| GPIO4 | 58 | I/O | |
| GPIO5 | 57 | I/O | |
| GPIO6 | 56 | I/O | |
| GPIO7 | 55 | I/O | |
| GPIO8 | 54 | I/O | |