ZHCSTD4B September 2019 – October 2023 BQ75614-Q1
PRODUCTION DATA
CURRENT_HI
| Address | 0x05D6 | |||||||
| Read Only | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
| Name | RESULT[7:0] | |||||||
| Reset | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| RESULT[7:0] = | The high-byte of the differential (SRP – SRN) in 2s complement from CS ADC. When host reads this register, the device locks the mid- and low-byte from update until the high-byte and low-byte registers are read. | |||||||
CURRENT_MID
| Address | 0x05D7 | |||||||
| Read Only | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
| Name | RESULT[7:0] | |||||||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| RESULT[7:0] = | The mid-byte of the differential (SRP – SRN) in 2s complement from CS ADC. | |||||||
CURRENT_LO
| Address | 0x05D8 | |||||||
| Read Only | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
| Name | RESULT[7:0] | |||||||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| RESULT[7:0] = | The low-byte of the differential (SRP – SRN) in 2s complement from CS ADC. | |||||||