ZHCSTD4B September 2019 – October 2023 BQ75614-Q1
PRODUCTION DATA
Once fault is detected, the fault status bit is latched until cleared using the reset bit. Similar to fault masking, when the specific fault reset bit is set, the associated low-level fault registers, including the DEBUG_* registers are cleared. The corresponding bit in the FAULT_SUMMARY register will clear if all its associated low-level registers are cleared. If the fault condition persists and the reset bit is written, the fault status bit is not reset. The fault indicator cannot be reset until the underlying fault condition is eliminated.
The fault is reset through the FAULT_RST1 and FAULT_RST2 registers; the fault reset bits are structured in the same corresponding fault status registers as the fault masking bits.