ZHCSGV6F June 2009 – January 2017 TMS320C6742
PRODUCTION DATA.
| NO. | 1.2V | 1.1V | 1.0V | UNIT | |||||
|---|---|---|---|---|---|---|---|---|---|
| MIN | MAX | MIN | MAX | MIN | MAX | ||||
| READS and WRITES | |||||||||
| E | tc(CLK) | Cycle time, EMIFA module clock | 6.75 | 13.33 | 20 | ns | |||
| 2 | tw(EM_WAIT) | Pulse duration, EM_WAIT assertion and deassertion | 2E | 2E | 2E | ns | |||
| READS | |||||||||
| 12 | tsu(EMDV-EMOEH) | Setup time, EM_D[15:0] valid before EM_OE high | 3 | 5 | 7 | ns | |||
| 13 | th(EMOEH-EMDIV) | Hold time, EM_D[15:0] valid after EM_OE high | 0 | 0 | 0 | ns | |||
| 14 | tsu(EMOEL-EMWAIT) | Setup Time, EM_WAIT asserted before end of Strobe Phase(2) | 4E+3 | 4E+3 | 4E+3 | ns | |||
| WRITES | |||||||||
| 28 | tsu(EMWEL-EMWAIT) | Setup Time, EM_WAIT asserted before end of Strobe Phase(2) | 4E+3 | 4E+3 | 4E+3 | ns | |||
| NO. | PARAMETER | 1.2V, 1.1V, 1.0V | UNIT | |||
|---|---|---|---|---|---|---|
| MIN | Nom | MAX | ||||
| READS and WRITES | ||||||
| 1 | td(TURNAROUND) | Turn around time | (TA)*E - 3 | (TA)*E | (TA)*E + 3 | ns |
| READS | ||||||
| 3 | tc(EMRCYCLE) | EMIF read cycle time (EW = 0) | (RS+RST+RH)*E - 3 | (RS+RST+RH)*E | (RS+RST+RH)*E + 3 | ns |
| EMIF read cycle time (EW = 1) | (RS+RST+RH+EWC)*E - 3 | (RS+RST+RH+EWC)*E | (RS+RST+RH+EWC)*E + 3 | ns | ||
| 4 | tsu(EMCEL-EMOEL) | Output setup time, EMA_CE[5:2] low to EMA_OE low (SS = 0) | (RS)*E-3 | (RS)*E | (RS)*E+3 | ns |
| Output setup time, EMA_CE[5:2] low to EMA_OE low (SS = 1) | -3 | 0 | +3 | ns | ||
| 5 | th(EMOEH-EMCEH) | Output hold time, EMA_OE high to EMA_CE[5:2] high (SS = 0) | (RH)*E - 3 | (RH)*E | (RH)*E + 3 | ns |
| Output hold time, EMA_OE high to EMA_CE[5:2] high (SS = 1) | -3 | 0 | +3 | ns | ||
| 6 | tsu(EMBAV-EMOEL) | Output setup time, EMA_BA[1:0] valid to EMA_OE low | (RS)*E-3 | (RS)*E | (RS)*E+3 | ns |
| 7 | th(EMOEH-EMBAIV) | Output hold time, EMA_OE high to EMA_BA[1:0] invalid | (RH)*E-3 | (RH)*E | (RH)*E+3 | ns |
| 8 | tsu(EMBAV-EMOEL) | Output setup time, EMA_A[13:0] valid to EMA_OE low | (RS)*E-3 | (RS)*E | (RS)*E+3 | ns |
| 9 | th(EMOEH-EMAIV) | Output hold time, EMA_OE high to EMA_A[13:0] invalid | (RH)*E-3 | (RH)*E | (RH)*E+3 | ns |
| 10 | tw(EMOEL) | EMA_OE active low width (EW = 0) | (RST)*E-3 | (RST)*E | (RST)*E+3 | ns |
| EMA_OE active low width (EW = 1) | (RST+EWC)*E-3 | (RST+EWC)*E | (RST+EWC)*E+3 | ns | ||
| 11 | td(EMWAITH-EMOEH) | Delay time from EMA_WAIT deasserted to EMA_OE high | 3E-3 | 4E | 4E+3 | ns |
| 28 | tsu(EMARW-EMOEL) | Output setup time, EMA_A_RW valid to EMA_OE low | (RS)*E-3 | (RS)*E | (RS)*E+3 | ns |
| 29 | th(EMOEH-EMARW) | Output hold time, EMA_OE high to EMA_A_RW invalid | (RH)*E-3 | (RH)*E | (RH)*E+3 | ns |
| WRITES | ||||||
| 15 | tc(EMWCYCLE) | EMIF write cycle time (EW = 0) | (WS+WST+WH)*E-3 | (WS+WST+WH)*E | (WS+WST+WH)*E+3 | ns |
| EMIF write cycle time (EW = 1) | (WS+WST+WH+EWC)*E - 3 | (WS+WST+WH+EWC)*E | (WS+WST+WH+EWC)*E + 3 | ns | ||
| 16 | tsu(EMCEL-EMWEL) | Output setup time, EMA_CE[5:2] low to EMA_WE low (SS = 0) | (WS)*E - 3 | (WS)*E | (WS)*E + 3 | ns |
| Output setup time, EMA_CE[5:2] low to EMA_WE low (SS = 1) | -3 | 0 | +3 | ns | ||
| 17 | th(EMWEH-EMCEH) | Output hold time, EMA_WE high to EMA_CE[5:2] high (SS = 0) | (WH)*E-3 | (WH)*E | (WH)*E+3 | ns |
| Output hold time, EMA_WE high to EMA_CE[5:2] high (SS = 1) | -3 | 0 | +3 | ns | ||
| 18 | tsu(EMDQMV-EMWEL) | Output setup time, EMA_BA[1:0] valid to EMA_WE low | (WS)*E-3 | (WS)*E | (WS)*E+3 | ns |
| 19 | th(EMWEH-EMDQMIV) | Output hold time, EMA_WE high to EMA_BA[1:0] invalid | (WH)*E-3 | (WH)*E | (WH)*E+3 | ns |
| 20 | tsu(EMBAV-EMWEL) | Output setup time, EMA_BA[1:0] valid to EMA_WE low | (WS)*E-3 | (WS)*E | (WS)*E+3 | ns |
| 21 | th(EMWEH-EMBAIV) | Output hold time, EMA_WE high to EMA_BA[1:0] invalid | (WH)*E-3 | (WH)*E | (WH)*E+3 | ns |
| 22 | tsu(EMAV-EMWEL) | Output setup time, EMA_A[13:0] valid to EMA_WE low | (WS)*E-3 | (WS)*E | (WS)*E+3 | ns |
| 23 | th(EMWEH-EMAIV) | Output hold time, EMA_WE high to EMA_A[13:0] invalid | (WH)*E-3 | (WH)*E | (WH)*E+3 | ns |
| 24 | tw(EMWEL) | EMA_WE active low width (EW = 0) | (WST)*E-3 | (WST)*E | (WST)*E+3 | ns |
| EMA_WE active low width (EW = 1) | (WST+EWC)*E-3 | (WST+EWC)*E | (WST+EWC)*E+3 | ns | ||
| 25 | td(EMWAITH-EMWEH) | Delay time from EMA_WAIT deasserted to EMA_WE high | 3E-3 | 4E | 4E+3 | ns |
| 26 | tsu(EMDV-EMWEL) | Output setup time, EMA_D[15:0] valid to EMA_WE low | (WS)*E-3 | (WS)*E | (WS)*E+3 | ns |
| 27 | th(EMWEH-EMDIV) | Output hold time, EMA_WE high to EMA_D[15:0] invalid | (WH)*E-3 | (WH)*E | (WH)*E+3 | ns |
| 30 | tsu(EMARW-EMWEL) | Output setup time, EMA_A_RW valid to EMA_WE low | (WS)*E-3 | (WS)*E | (WS)*E+3 | ns |
| 31 | th(EMWEH-EMARW) | Output hold time, EMA_WE high to EMA_A_RW invalid | (WH)*E-3 | (WH)*E | (WH)*E+3 | ns |
Figure 6-14 Asynchronous Memory Read Timing for EMIFA
Figure 6-15 Asynchronous Memory Write Timing for EMIFA
Figure 6-16 EMA_WAIT Read Timing Requirements
Figure 6-17 EMA_WAIT Write Timing Requirements