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ZHCSGV6F June 2009 – January 2017 TMS320C6742

PRODUCTION DATA.

封裝選項(xiàng)

請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。

機(jī)械數(shù)據(jù) (封裝 | 引腳)

ZWT|361

散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)

訂購信息

3.7.2 High-Frequency Oscillator and PLL

Table 3-6 High-Frequency Oscillator and PLL Terminal Functions

SIGNAL		TYPE⁽¹⁾	PULL⁽²⁾	POWER GROUP⁽³⁾	DESCRIPTION
NAME	NO.	TYPE⁽¹⁾	PULL⁽²⁾	POWER GROUP⁽³⁾	DESCRIPTION
CLKOUT / UHPI_HDS2 / GP6[14]	T18	O	CP[22]	C	PLL Observation Clock⁽⁴⁾
1.2-V OSCILLATOR
OSCIN	L19	I	—	—	Oscillator input
OSCOUT	K19	O	—	—	Oscillator output
OSCVSS	L18	GND	—	—	Oscillator ground
1.2-V PLL0
PLL0_VDDA	L15	PWR	—	—	PLL analog V_DD (1.2-V filtered supply)
PLL0_VSSA	M17	GND	—	—	PLL analog V_SS (for filter)
1.2-V PLL1
PLL1_VDDA	N15	PWR	—	—	PLL analog V_DD (1.2-V filtered supply)
PLL1_VSSA	M15	GND	—	—	PLL analog V_SS (for filter)

(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.

(2) IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using the PUPDENA and PUPDSEL registers in the System Module. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see the Device Configuration section. For electrical specifications on pullup and internal pulldown circuits, see the Device Operating Conditions section.

(3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power supply DVDD3318_C.

(4) Note: The CLKOUT clock output is provided as PLL observation clock, and is provided for debug purposes only. It may be routed to a test point, but should never be connected to a load.