ZHCSGV6F June 2009 – January 2017 TMS320C6742
PRODUCTION DATA.
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
| NO. | PARAMETER | 1.2V | 1.1V | 1.0V | UNIT | |||||
|---|---|---|---|---|---|---|---|---|---|---|
| MIN | MAX | MIN | MAX | MIN | MAX | |||||
| 17 | td(EN A_SPC)M | Delay from slave assertion of SPI1_ENA active to first SPI1_CLK from master.(3) | Polarity = 0, Phase = 0,
to SPI1_CLK rising |
3P+5 | 3P+5 | 3P+6 | ns | |||
| Polarity = 0, Phase = 1,
to SPI1_CLK rising |
0.5M+3P+5 | 0.5M+3P+5 | 0.5M+3P+6 | |||||||
| Polarity = 1, Phase = 0,
to SPI1_CLK falling |
3P+5 | 3P+5 | 3P+6 | |||||||
| Polarity = 1, Phase = 1,
to SPI1_CLK falling |
0.5M+3P+5 | 0.5M+3P+5 | 0.5M+3P+6 | |||||||
| 18 | td(SPC_ENA)M | Max delay for slave to deassert SPI1_ENA after final SPI1_CLK edge to ensure master does not begin the next transfer.(4) | Polarity = 0, Phase = 0,
from SPI1_CLK falling |
0.5M+P+5 | 0.5M+P+5 | 0.5M+P+6 | ns | |||
| Polarity = 0, Phase = 1,
from SPI1_CLK falling |
P+5 | P+5 | P+6 | |||||||
| Polarity = 1, Phase = 0,
from SPI1_CLK rising |
0.5M+P+5 | 0.5M+P+5 | 0.5M+P+6 | |||||||
| Polarity = 1, Phase = 1,
from SPI1_CLK rising |
P+5 | P+5 | P+6 | |||||||