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ZHCSGV6F June 2009 – January 2017 TMS320C6742

PRODUCTION DATA.

封裝選項

請參考 PDF 數據表獲取器件具體的封裝圖。

機械數據 (封裝 | 引腳)

ZWT|361

散熱焊盤機械數據 (封裝 | 引腳)

訂購信息

6.11.3.11 DDR2/mDDR CK and ADDR_CTRL Routing

Figure 6-23 shows the topology of the routing for the CK and ADDR_CTRL net classes. The route is a balanced T as it is intended that the length of segments B and C be equal. In addition, the length of A should be maximized.

Figure 6-23 CK and ADDR_CTRL Routing and Topology

Table 6-34 CK and ADDR_CTRL Routing Specification

NO.	PARAMETER	MIN	TYP	MAX	UNIT
1	Center to Center CK-CKN Spacing⁽³⁾			2w⁽⁴⁾
2	CK A to B/A to C Skew Length Mismatch⁽¹⁾			25	Mils
3	CK B to C Skew Length Mismatch			25	Mils
4	Center to center CK to other DDR2/mDDR trace spacing⁽³⁾	4w⁽⁴⁾
5	CK/ADDR_CTRL nominal trace length⁽²⁾	CACLM-50	CACLM	CACLM+50	Mils
6	ADDR_CTRL to CK Skew Length Mismatch			100	Mils
7	ADDR_CTRL to ADDR_CTRL Skew Length Mismatch			100	Mils
8	Center to center ADDR_CTRL to other DDR2/mDDR trace spacing⁽³⁾	4w⁽⁴⁾
9	Center to center ADDR_CTRL to other ADDR_CTRL trace spacing⁽³⁾	3w ⁽⁴⁾
10	ADDR_CTRL A to B/A to C Skew Length Mismatch⁽¹⁾			100	Mils
11	ADDR_CTRL B to C Skew Length Mismatch			100	Mils

(1) Series terminator, if used, should be located closest to device.

(2) CACLM is the longest Manhattan distance of the CK and ADDR_CTRL net classes.

(3) Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing congestion.

(4) w = PCB trace width as defined in Table 6-27.

Figure 6-24 shows the topology and routing for the DQS and D net class; the routes are point to point. Skew matching across bytes is not needed nor recommended.

Figure 6-24 DQS and D Routing and Topology

Table 6-35 DQS and D Routing Specification

NO.	PARAMETER	MIN	TYP	MAX	UNIT
1	Center to center DQS to other DDR2/mDDR trace spacing⁽⁴⁾	4w⁽⁶⁾
2	DQS/D nominal trace length⁽¹⁾⁽³⁾	DQLM-50	DQLM	DQLM+50	Mils
3	D to DQS Skew Length Mismatch⁽³⁾			100	Mils
4	D to D Skew Length Mismatch⁽³⁾			100	Mils
5	Center to center D to other DDR2/mDDR trace spacing⁽⁴⁾⁽⁵⁾	4w⁽⁶⁾
6	Center to Center D to other D trace spacing⁽⁴⁾⁽²⁾	3w⁽⁶⁾

(1) Series terminator, if used, should be located closest to DDR.

(2) DQLM is the longest Manhattan distance of each of the DQS and D net class.

(3) There is no need and it is not recommended to skew match across data bytes, i.e., from DQS0 and data byte 0 to DQS1 and data byte 1.

(4) Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing congestion.

(5) D's from other DQS domains are considered other DDR2/mDDR trace.

(6) w = PCB trace width as defined in Table 6-27.

Figure 6-25 shows the routing for the DQGATE net class. Table 6-36 contains the routing specification.

Figure 6-25 DQGATE Routing

Table 6-36 DQGATE Routing Specification

NO.	PARAMETER	MIN	TYP	MAX	UNIT
1	DQGATE Length F		CKB0B⁽¹⁾
2	Center to center DQGATE to any other trace spacing	4w⁽³⁾
3	DQS/D nominal trace length	DQLM-50	DQLM	DQLM+50	Mils
4	DQGATE Skew⁽²⁾			100	Mils

(1) CKB0B1 is the sum of the length of the CK net plus the average length of the DQS0 and DQS1 nets.

(2) Skew from CKB0B1

(3) w = PCB trace width as defined in Table 6-27.