ZHCSGP5C August 2017 – February 2022 TIC12400-Q1
PRODUCTION DATA
The SO pin is the output from the internal shift register. The SO pin remains high-impedance until the CS pin transitions to a logic LOW state. The negative transition of CS enables the SO output driver and drives the SO output to the HIGH state (by default). The first positive transition of SCLK makes the status data bit 31 available on the SO pin. Each successive positive clock makes the next status data bit available for the microcontroller to read on the falling edge of SCLK. The SI/SO shifting of the data follows a first-in, first-out scheme, with both input and output words transferring the most significant bit (MSB) first.