ZHCSGP5C August 2017 – February 2022 TIC12400-Q1
PRODUCTION DATA
The Read/Write bit (bit 31) on the SI bus needs to be set to 1 for a write operation. The 6-bits address of the register to be accessed follows next on the SI bus. Note: the register needs to be a writable configuration register, or otherwise the command will be ignored. The content from bit 24 to bit 1 represents the data to be written to the register. The LSB (bit 0) is the parity bit used to detect communication errors.
On the SO bus, the status flags will be output from the TIC12400-Q1, followed by the previous data content of the written register. The previous content of the register is latched after the full register address is decoded in the SI command (after bit 25 is transmitted). The new data will replace the previous data content at the end of the SPI transaction if the SI write is a valid command (valid register address and no SPI/parity error). If the write command is invalid, the new data will be ignored and the register content will remain unchanged. The LSB is the parity bit used to detect communication errors.
Note: there are several test mode registers used in the TIC12400-Q1 in addition to the normal functional registers. A WRITE command to these test registers has no effect on the register content, even though the register content is returned on the SO output. If a WRITE command is issued to an invalid register address, the SO output returns all 0s.