ZHCSGP5C August 2017 – February 2022 TIC12400-Q1
PRODUCTION DATA
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Parameter Measurement Information
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 VS Pin
- 8.3.2 VDD Pin
- 8.3.3 Device Initialization
- 8.3.4 Device Trigger
- 8.3.5 Device Reset
- 8.3.6 VS Under-Voltage (UV) Condition
- 8.3.7 VS Over-Voltage (OV) Condition
- 8.3.8 Switch Inputs Settings
- 8.3.9 Interrupt Generation and INT Assertion
- 8.3.10 Temperature Monitor
- 8.3.11 Parity Check and Parity Generation
- 8.3.12 Cyclic Redundancy Check (CRC)
- 8.4 Device Functional Modes
- 8.5 Programming
- 8.6 Register Maps
- 8.7 Programming Guidelines
- 9 Application Information Disclaimer
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
8.3.9.2 Interrupt Idle Time (tINT_IDLE) Time
Interrupt idle time (tINT_IDLE) is implemented in TIC12400-Q1 to:
- Allow the INT pin enough time to be pulled back high by the external pull-up resistor and allow the next assertion to be detectable by an edge-triggered microcontroller.
- Minimize the chance of glitching on the INT pin if back-to-back events occur.
When there is a pending interrupt event and the interrupt event is not masked, tINT_IDLE is applied after the READ command is issued to the INT_STAT register. If another event occurs during the interrupt idle time the INT_STAT register content is updated instantly but the INT pin is not asserted low until tINT_IDLE has elapsed. If another READ command is issued to the INT_STAT register during tINT_IDLE, the INT_STAT register content is cleared immediately, but the INT pin is not re-asserted back low after tINT_IDLE has elapsed. An example of the interrupt idle time is given below to illustrate the INT pin behavior under the static INT assertion schemes:
Figure 8-8 INT Assertion Scheme With tINT_IDLE