ZHCSGP5C August 2017 – February 2022 TIC12400-Q1
PRODUCTION DATA
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Parameter Measurement Information
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 VS Pin
- 8.3.2 VDD Pin
- 8.3.3 Device Initialization
- 8.3.4 Device Trigger
- 8.3.5 Device Reset
- 8.3.6 VS Under-Voltage (UV) Condition
- 8.3.7 VS Over-Voltage (OV) Condition
- 8.3.8 Switch Inputs Settings
- 8.3.9 Interrupt Generation and INT Assertion
- 8.3.10 Temperature Monitor
- 8.3.11 Parity Check and Parity Generation
- 8.3.12 Cyclic Redundancy Check (CRC)
- 8.4 Device Functional Modes
- 8.5 Programming
- 8.6 Register Maps
- 8.7 Programming Guidelines
- 9 Application Information Disclaimer
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
12.4 Electrostatic Discharge Caution
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. |
| ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. |