ZHCSF47E June 2016 – December 2017 TAS2560
PRODUCTION DATA.
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
D Ramp Control
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RAMP_MODE[1:0] | RAMP_FREQ[1:0] | Reserved | RAMP_FREQMOD[1:0] | ||||
| RW-0h | RW-0h | RW-0h | RW-1h | ||||
| LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-6 | RAMP_MODE[1:0] | RW | 0h | The Class-D ramp clock mode
0 = SYNC, generated from digital audio stream 1 = FFM, generated from internal oscillator 2 = SSM, generated from internal oscillator with spread-spectrum 3 = Reserved |
| 5-4 | RAMP_FREQ[1:0] | RW | 0h | The ramp frequency is
0 = 348kHz (Use for Fs=48ksps and multiples) 1 = 352.8kHz (Use for Fs=44.1ksps and multiples) 2 = Reserved |
| 3-2 | Reserved | RW | 0h | Reserved |
| 1-0 | RAMP_FREQMOD[1:0] | RW | 0h | Sets the ramp frequency modulation rate or to a fixed offset.
0 = Reserved 1 = Set the SSM to 5% frequency modulation 2 = Set the SSM to 10% frequency modulation 3 = Reserved |