ZHCSF47E June 2016 – December 2017 TAS2560
PRODUCTION DATA.
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
Clock Error and DSP memory Reload
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DSP_MEMRST | Reserved | Reserved | CLK_E1_SRC | CLK_E2_SRC[1:0] | CLK_E1_EN | CLK_E2_EN | |
| RW-0h | RW-0h | RW-0h | RW-0h | RW-0h | RW-1h | RW-1h | |
| LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | DSP_MEMRST | RW | 0h | Determine if the DSP memory locations will be reloaded for reasons other than user power down such as clock-halt, brownout, over current, over temp, and over voltage.
0 = Do not reload on restart 1 = Reload defaults on restart |
| 6 | Reserved | RW | 0h | Reserved |
| 5 | Reserved | RW | 0h | Reserved |
| 4 | CLK_E1_SRC | RW | 0h | Clock error detection 1 block input is from
0 = ASI_CLK 1 = PDM_CLK |
| 3-2 | CLK_E2_SRC[1:0] | RW | 0h | Clock error detection 2 block input is from
0 = DAC Modulator Clock 1 = ADC Modulator Clock 2 = PLL Clock 3 = Reserved |
| 1 | CLK_E1_EN | RW | 0h | Clock error detection block 1 is
0 = Disabled 1 = Enabled |
| 0 | CLK_E2_EN | RW | 0h | Clock error detection block 2 is
0 = Disabled 1 = Enabled |