ZHCSF47E June 2016 – December 2017 TAS2560
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
-
7 Specifications
- 7.1 Absolute Maximum Ratings
- 7.2 ESD Ratings
- 7.3 Recommended Operating Conditions
- 7.4 Thermal Information
- 7.5 Electrical Characteristics
- 7.6 I2C Timing Requirements
- 7.7 I2S/LJF/RJF Timing in Master Mode
- 7.8 I2S/LJF/RJF Timing in Slave Mode
- 7.9 DSP Timing in Master Mode
- 7.10 DSP Timing in Slave Mode
- 7.11 PDM Timing
- 7.12 Typical Characteristics
- 8 Parameter Measurement Information
-
9 Detailed Description
- 9.1 Overview
- 9.2 Functional Block Diagram
- 9.3
Feature Description
- 9.3.1 General I2C Operation
- 9.3.2 Single-Byte and Multiple-Byte Transfers
- 9.3.3 Single-Byte Write
- 9.3.4 Multiple-Byte Write and Incremental Multiple-Byte Write
- 9.3.5 Single-Byte Read
- 9.3.6 Multiple-Byte Read
- 9.3.7 PLL
- 9.3.8 Clock Distribution
- 9.3.9 Clock Error Detection
- 9.3.10 Class-D Edge Rate Control
- 9.3.11 IV Sense
- 9.3.12 Boost Control
- 9.3.13 Thermal Fold-back
- 9.3.14 Battery Guard AGC
- 9.3.15 Configurable Boost Current Limit (ILIM)
- 9.3.16 Fault Protection
- 9.3.17 Spread Spectrum vs Synchronized
- 9.3.18 IRQs and Flags
- 9.3.19 CRC checksum for I2C
- 9.3.20 PurePath Console 3 Software TAS2560 Application
- 9.4 Device Functional Modes
- 9.5 Operational Modes
- 9.6 Programming
- 9.7
Register Map
- 9.7.1 Register Map Summary
- 9.7.2 PAGE (book=0x00 page=0x00 address=0x00) [reset=0h]
- 9.7.3 RESET (book=0x00 page=0x00 address=0x01) [reset=0h]
- 9.7.4 MODE (book=0x00 page=0x00 address=0x02) [reset=1h]
- 9.7.5 SPK_CTRL (book=0x00 page=0x00 address=0x04) [reset=5Fh]
- 9.7.6 PWR_CTRL_2 (book=0x00 page=0x00 address=0x05) [reset=0h]
- 9.7.7 PWR_CTRL_1 (book=0x00 page=0x00 address=0x07) [reset=0h]
- 9.7.8 RAMP_CTRL (book=0x00 page=0x00 address=0x08) [reset=1h]
- 9.7.9 EDGE_ISNS_BOOST (book=0x00 page=0x00 address=0x09) [reset=83h]
- 9.7.10 PLL_CLKIN (book=0x00 page=0x00 address=0x0F) [reset=41h]
- 9.7.11 PLL_JVAL (book=0x00 page=0x00 address=0x10) [reset=4h]
- 9.7.12 PLL_DVAL_1 (book=0x00 page=0x00 address=0x11) [reset=0h]
- 9.7.13 PLL_DVAL_2 (book=0x00 page=0x00 address=0x12) [reset=0h]
- 9.7.14 ASI_FORMAT (book=0x00 page=0x00 address=0x14) [reset=2h]
- 9.7.15 ASI_CHANNEL (book=0x00 page=0x00 address=0x15) [reset=0h]
- 9.7.16 ASI_OFFSET_1 (book=0x00 page=0x00 address=0x16) [reset=0h]
- 9.7.17 ASI_OFFSET_2 (book=0x00 page=0x00 address=0x17) [reset=0h]
- 9.7.18 ASI_CFG_1 (book=0x00 page=0x00 address=0x18) [reset=0h]
- 9.7.19 ASI_DIV_SRC (book=0x00 page=0x00 address=0x19) [reset=0h]
- 9.7.20 ASI_BDIV (book=0x00 page=0x00 address=0x1A) [reset=1h]
- 9.7.21 ASI_WDIV (book=0x00 page=0x00 address=0x1B) [reset=40h]
- 9.7.22 PDM_CFG (book=0x00 page=0x00 address=0x1C) [reset=0h]
- 9.7.23 PDM_DIV (book=0x00 page=0x00 address=0x1D) [reset=8h]
- 9.7.24 DSD_DIV (book=0x00 page=0x00 address=0x1E) [reset=8h]
- 9.7.25 CLK_ERR_1 (book=0x00 page=0x00 address=0x21) [reset=3h]
- 9.7.26 CLK_ERR_2 (book=0x00 page=0x00 address=0x22) [reset=3Fh]
- 9.7.27 IRQ_PIN_CFG (book=0x00 page=0x00 address=0x23) [reset=21h]
- 9.7.28 INT_CFG_1 (book=0x00 page=0x00 address=0x24) [reset=0h]
- 9.7.29 INT_CFG_2 (book=0x00 page=0x00 address=0x25) [reset=0h]
- 9.7.30 INT_DET_1 (book=0x00 page=0x00 address=0x26) [reset=0h]
- 9.7.31 INT_DET_2 (book=0x00 page=0x00 address=0x27) [reset=0h]
- 9.7.32 STATUS_POWER (book=0x00 page=0x00 address=0x2A) [reset=0h]
- 9.7.33 SAR_VBAT_MSB (book=0x00 page=0x00 address=0x2D) [reset=C0h]
- 9.7.34 SAR_VBAT_LSB (book=0x00 page=0x00 address=0x2E) [reset=0h]
- 9.7.35 DIE_TEMP_SENSOR (book=0x00 page=0x00 address=0x31) [reset=0h]
- 9.7.36 LOW_PWR_MODE (book=0x00 page=0x00 address=0x35) [reset=0h]
- 9.7.37 PCM_RATE (book=0x00 page=0x00 address=0x36) [reset=32h]
- 9.7.38 CLOCK_ERR_CFG_1 (book=0x00 page=0x00 address=0x4F) [reset=0h]
- 9.7.39 CLOCK_ERR_CFG_2 (book=0x00 page=0x00 address=0x50) [reset=11h]
- 9.7.40 PROTECTION_CFG_1 (book=0x00 page=0x00 address=0x58) [reset=3h]
- 9.7.41 CRC_CHECKSUM (book=0x00 page=0x00 address=0x7E) [reset=0h]
- 9.7.42 BOOK (book=0x00 page=0x00 address=0x7F) [reset=0h]
- 10Application and Implementation
- 11Power Supply Recommendations
- 12Layout
- 13器件和文檔支持
- 14機械、封裝和可訂購信息
9.3.7 PLL
The TAS2560 on-chip PLL generates the necessary internal clock frequency for the audio DAC, I-V sensing ADCs, and DSP. The programmability of the PLL allows TAS2560 operation from a wide variety of clocks that may be available in the system application. The configurable PLL clock path is shown in Figure 30.
Figure 30. PLL_CLK Source and Generation
The PLL input supports clocks varying from 512 kHz to 20 MHz and is register programmable to enable generation of required PLL_CLK from various clocks with fine resolution. The PLL output clock PLL_CLK is determined from PLL_CLKIN using the following formula:
The PLL multipliers and dividers are program using the register in Table 2. The table includes also the range of values support and the default values. The D-divider value is 14-bits wide and is controlled by 2 registers. For proper update of the D-divider value, PLL_DVAL_1 must be programmed first followed immediately by PLL_DVAL_2. Unless the write to PLL_DVAL_2 is completed, the new value of D will not take effect.
Table 2. PLL Scaling Registers
| PLL Divider | Register Name | Field | Range | Default |
|---|---|---|---|---|
| J | PLL_JVAL[6:0] | PLL_MULT_J | 1, 2, 3, … 63 | 4 |
| D | PLL_DVAL_1[5:0] & PLL_DVAL_2[7:0] | PLL_MULT_D | 0, 1, 2, ... 9999 | 0 |
| P | PLL_CLKIN[5:0] | PLL_P_DIV | 64,1,2,3, ... 63 | 1 |
Field PLL_CLK_SRC in register PLL_CLKIN configures the PLL clock input, PLL_CLKIN.
Table 3. PLL Clock Input Source
| PLL_CLKIN[7:6] (PLL_CLK_SRC) | PLL_CLKIN Source |
|---|---|
| 00 | Input from BCLK |
| 01 | Input from MCLK (default) |
| 10 | Input from PDMLK |
| 11 | Reserved |
The following conditions must be satisfied in the PLL configuration:
- If D = 0 (Integer Mode), the PLL clock input (PLL_CLKIN) must satisfy:
- If D > 0(Fractional Mode), the PLL clock input (PLL_CLKIN) must satisfy:
- The PLL output needs to be configured between 100 MHz and 200 MHz
Finally, the PLL_LOWF field in register PLL_JVAL must be configured properly based on the PLL_INPUT_CLK intermediate clock frequency.
Table 4. PLL Clock Input Source
| PLL_JVAL[7] (PLL_LOWF) | PLL_INPUT_CLK Condition |
|---|---|
| 0 | >= 1MHz (default) |
| 1 | < 1MHz |