9.4.1 Audio Digital I/O Interface
Audio data is transferred between the host processor and the TAS2560 via the digital audio serial interface(ASI), or audio bus. The audio bus on this device is flexible, including left or right-justified data options, support for I2S or PCM protocols, programmable data length options, a TDM mode for multichannel operation, very flexible master/slave configurability for each bus clock line, and the ability to communicate with multiple devices within a system directly. The audio bus of the TAS2560, when using PCM formatted input and/or output, can be configured for left or right-justified, I2S, DSP, or TDM modes of operation, where communication with standard telephony PCM interfaces is supported within the TDM mode. These modes are all MSB-first, with data width programmable as 16, 20, 24, or 32 bits where the chip input can be left, right or L+R/2.
Table 30. ASI PCM Input Word Length
| ASI_FORMAT[1:0] (ASI_LENGTH) |
Word Length |
| 00 |
16 bits |
| 01 |
20 bits |
| 10 |
24 bits (default) |
| 11 |
32 bits |
Table 31. ASI PCM Channel Mode
| ASI_CHANNEL[1:0] (ASI_CHAN_MODE) |
Input Stereo Channel |
| 00 |
Left (default) |
| 01 |
Right |
| 10 |
(Left + Right) / 2 |
| 11 |
monoPCM |
In addition, the word clock and bit clock can be independently configured in either Master or Slave mode, for flexible connectivity to a wide variety of processors. The word clock is used to define the beginning of a frame, and may be programmed as either a pulse(DSP) or a 50% duty cycle signal(I2S). The frequency of this clock corresponds to the maximum of the selected ADC and DAC sampling frequencies. Clock sources for Master mode are described in section Clock Distribution. When the audio serial data bus is powered down while configured in master mode, the terminals associated with the interface are put into a Hi-Z output state.
Table 32. ASI WCLK Mode
| ASI_CFG_1[5] (ASI_WCLKM) |
WCLK Mode |
| 0 |
Input - Slave Mode (default) |
| 1 |
Output - Master Mode |
Table 33. ASI WCLK Edge
| ASI_CFG_1[3] (ASI_WCLKE) |
WCLK Edge |
| 0 |
As per the timing spec (default) |
| 1 |
Inverted with respect to timing spec |
Table 34. ASI Dividers Clock Source
| ASI_DIV_SRC[1:0] (ASI_DIV_CLK_SRC) |
Input Stereo Channel |
| 00 |
DAC_MOD_CLK (default) |
| 01 |
ADC_MOD_CLK |
| 10 |
NDIV_CLK |
| 11 |
Reserved |
Table 35. ASI WCLK Divider Power
| ASI_WDIV[7] (ASI_WDIV_P) |
WCLK Divider Power |
| 0 |
Powered Down (default) |
| 1 |
Powered Up |
Table 36. ASI WCLK Divider Ratio
| ASI_WDIV[6:0] (ASI_WDIV_RATIO) |
WCLK Divider Ratio |
| 0x00 |
128 |
| 0x01-0x1F |
Reserved |
| 0x20 |
32 |
| ... |
... |
| 0x40 |
64 (default) |
| ... |
... |
| 0x7F |
127 |
The bit clock is used to clock-in and clock-out the digital audio data across the serial bus. This signal can be programmed to generate variable clock pulses by controlling the bit-clock multiply-divide factor. The number of bit-clock pulses in a frame may need adjustment to accommodate various word-lengths as well as to support the case when multiple TAS2560 devices may share the same audio bus.
Table 37. ASI BCLK Mode
| ASI_CFG_1[4] (ASI_BCLKM) |
BCLK Mode |
| 0 |
Input - Slave Mode (default) |
| 1 |
Output - Master Mode |
Table 38. ASI BCLK Edge
| ASI_CFG_1[2] (ASI_BCLKE) |
BCLK Edge |
| 0 |
As per the timing spec (default) |
| 1 |
Inverted with respect to timing spec |
Table 39. ASI BCLK Divider Power
| ASI_BDIV[7] (ASI_WDIV_P) |
BCLK Divider Power |
| 0 |
Powered Down (default) |
| 1 |
Powered Up |
Table 40. ASI BCLK Divider Ratio
| ASI_BDIV[6:0] (ASI_WDIV_RATIO) |
BCLK Divider Ratio |
| 0x00 |
128 |
| 0x01 |
1 (default) |
| 0x02 |
2 |
| ... |
... |
| 0x7F |
127 |
The TAS2560 also includes a feature to offset the position of start of data transfer with respect to the word-clock(WCLK). This offset is specified in number of bit-clocks. This can be used in cases where there is a non-zero bit-clock delay from WCLK edge or to support TDM modes of operation. The TAS2560 can place the DOUT line into a Hi-Z (tri-state) condition during all bit clocks when valid data is not being sent. TDM mode is useable with I2S, LJF, RJF, and DSP interface modes and is required for stereo applications when more than one TAS2560 part is used, see Stereo Application Example - TDM Mode. The TAS2560 also has a bus keeper circuit that can be enabled in tri-sate mode. The bus-keeper is a weak internal latch that will hold the data line state without the need for external pull-up or pull-down resistors while signal lines are in the Hi-Z or non-driven state.
Table 41. ASI OFFSET1
| ASI_OFFSET_1 (ASI_OFFSET1) |
BCLKs from WCLK edge for data channel |
| 0x00 |
0 (default) |
| 0x01 |
1 |
| 0x02 |
2 |
| ... |
... |
| 0xFF |
255 |
Table 42. ASI Tri-state
| ASI_CFG_1[1] (ASI_TRISTATE) |
Tri-state DOUT for extra BCLK cycles after frame is complete |
| 0 |
disabled (default) |
| 1 |
enabled |
Table 43. ASI Bus-keeper
| ASI_CFG_1[0] (ASI_BUSKEEP) |
Tri-state DOUT for extra BCLK cycles after frame is complete |
| 0 |
disabled (default) |
| 1 |
enabled |