ZHCSF47E June 2016 – December 2017 TAS2560
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
-
7 Specifications
- 7.1 Absolute Maximum Ratings
- 7.2 ESD Ratings
- 7.3 Recommended Operating Conditions
- 7.4 Thermal Information
- 7.5 Electrical Characteristics
- 7.6 I2C Timing Requirements
- 7.7 I2S/LJF/RJF Timing in Master Mode
- 7.8 I2S/LJF/RJF Timing in Slave Mode
- 7.9 DSP Timing in Master Mode
- 7.10 DSP Timing in Slave Mode
- 7.11 PDM Timing
- 7.12 Typical Characteristics
- 8 Parameter Measurement Information
-
9 Detailed Description
- 9.1 Overview
- 9.2 Functional Block Diagram
- 9.3
Feature Description
- 9.3.1 General I2C Operation
- 9.3.2 Single-Byte and Multiple-Byte Transfers
- 9.3.3 Single-Byte Write
- 9.3.4 Multiple-Byte Write and Incremental Multiple-Byte Write
- 9.3.5 Single-Byte Read
- 9.3.6 Multiple-Byte Read
- 9.3.7 PLL
- 9.3.8 Clock Distribution
- 9.3.9 Clock Error Detection
- 9.3.10 Class-D Edge Rate Control
- 9.3.11 IV Sense
- 9.3.12 Boost Control
- 9.3.13 Thermal Fold-back
- 9.3.14 Battery Guard AGC
- 9.3.15 Configurable Boost Current Limit (ILIM)
- 9.3.16 Fault Protection
- 9.3.17 Spread Spectrum vs Synchronized
- 9.3.18 IRQs and Flags
- 9.3.19 CRC checksum for I2C
- 9.3.20 PurePath Console 3 Software TAS2560 Application
- 9.4 Device Functional Modes
- 9.5 Operational Modes
- 9.6 Programming
- 9.7
Register Map
- 9.7.1 Register Map Summary
- 9.7.2 PAGE (book=0x00 page=0x00 address=0x00) [reset=0h]
- 9.7.3 RESET (book=0x00 page=0x00 address=0x01) [reset=0h]
- 9.7.4 MODE (book=0x00 page=0x00 address=0x02) [reset=1h]
- 9.7.5 SPK_CTRL (book=0x00 page=0x00 address=0x04) [reset=5Fh]
- 9.7.6 PWR_CTRL_2 (book=0x00 page=0x00 address=0x05) [reset=0h]
- 9.7.7 PWR_CTRL_1 (book=0x00 page=0x00 address=0x07) [reset=0h]
- 9.7.8 RAMP_CTRL (book=0x00 page=0x00 address=0x08) [reset=1h]
- 9.7.9 EDGE_ISNS_BOOST (book=0x00 page=0x00 address=0x09) [reset=83h]
- 9.7.10 PLL_CLKIN (book=0x00 page=0x00 address=0x0F) [reset=41h]
- 9.7.11 PLL_JVAL (book=0x00 page=0x00 address=0x10) [reset=4h]
- 9.7.12 PLL_DVAL_1 (book=0x00 page=0x00 address=0x11) [reset=0h]
- 9.7.13 PLL_DVAL_2 (book=0x00 page=0x00 address=0x12) [reset=0h]
- 9.7.14 ASI_FORMAT (book=0x00 page=0x00 address=0x14) [reset=2h]
- 9.7.15 ASI_CHANNEL (book=0x00 page=0x00 address=0x15) [reset=0h]
- 9.7.16 ASI_OFFSET_1 (book=0x00 page=0x00 address=0x16) [reset=0h]
- 9.7.17 ASI_OFFSET_2 (book=0x00 page=0x00 address=0x17) [reset=0h]
- 9.7.18 ASI_CFG_1 (book=0x00 page=0x00 address=0x18) [reset=0h]
- 9.7.19 ASI_DIV_SRC (book=0x00 page=0x00 address=0x19) [reset=0h]
- 9.7.20 ASI_BDIV (book=0x00 page=0x00 address=0x1A) [reset=1h]
- 9.7.21 ASI_WDIV (book=0x00 page=0x00 address=0x1B) [reset=40h]
- 9.7.22 PDM_CFG (book=0x00 page=0x00 address=0x1C) [reset=0h]
- 9.7.23 PDM_DIV (book=0x00 page=0x00 address=0x1D) [reset=8h]
- 9.7.24 DSD_DIV (book=0x00 page=0x00 address=0x1E) [reset=8h]
- 9.7.25 CLK_ERR_1 (book=0x00 page=0x00 address=0x21) [reset=3h]
- 9.7.26 CLK_ERR_2 (book=0x00 page=0x00 address=0x22) [reset=3Fh]
- 9.7.27 IRQ_PIN_CFG (book=0x00 page=0x00 address=0x23) [reset=21h]
- 9.7.28 INT_CFG_1 (book=0x00 page=0x00 address=0x24) [reset=0h]
- 9.7.29 INT_CFG_2 (book=0x00 page=0x00 address=0x25) [reset=0h]
- 9.7.30 INT_DET_1 (book=0x00 page=0x00 address=0x26) [reset=0h]
- 9.7.31 INT_DET_2 (book=0x00 page=0x00 address=0x27) [reset=0h]
- 9.7.32 STATUS_POWER (book=0x00 page=0x00 address=0x2A) [reset=0h]
- 9.7.33 SAR_VBAT_MSB (book=0x00 page=0x00 address=0x2D) [reset=C0h]
- 9.7.34 SAR_VBAT_LSB (book=0x00 page=0x00 address=0x2E) [reset=0h]
- 9.7.35 DIE_TEMP_SENSOR (book=0x00 page=0x00 address=0x31) [reset=0h]
- 9.7.36 LOW_PWR_MODE (book=0x00 page=0x00 address=0x35) [reset=0h]
- 9.7.37 PCM_RATE (book=0x00 page=0x00 address=0x36) [reset=32h]
- 9.7.38 CLOCK_ERR_CFG_1 (book=0x00 page=0x00 address=0x4F) [reset=0h]
- 9.7.39 CLOCK_ERR_CFG_2 (book=0x00 page=0x00 address=0x50) [reset=11h]
- 9.7.40 PROTECTION_CFG_1 (book=0x00 page=0x00 address=0x58) [reset=3h]
- 9.7.41 CRC_CHECKSUM (book=0x00 page=0x00 address=0x7E) [reset=0h]
- 9.7.42 BOOK (book=0x00 page=0x00 address=0x7F) [reset=0h]
- 10Application and Implementation
- 11Power Supply Recommendations
- 12Layout
- 13器件和文檔支持
- 14機械、封裝和可訂購信息
9.3.14 Battery Guard AGC
The TAS2560 monitors battery voltage and the audio signal to automatically decrease gain when the battery voltage is low and audio output power is high. This provides louder audio while preventing early shutdown at end-of-charge battery voltage levels. The battery tracking AGC starts to attenuate the signal once the voltage at the Class-D output exceeds VLIM for a given battery voltage (VBAT). If the Class-D output voltage is below the VLIM value, no attenuation occurs. If the Class-D output exceeds the VLIM value the AGC starts to attack the signal and reduce the gain until the output is reduced to VLIM. Once the signal returns below VLIM plus some hysteresis the gain reduction decays. The VLIM is constant above the user configurable inflection point. Below the inflection point the VLIM is reduced by a user configurable slope in relation to the battery voltage. The attack time, decay time, hysteresis, inflection point and VLIM/VBAT slope below the inflection point are user configurable. The parameters for the Battery Tracking AGC are part of the DSP core and can be set using the PurePath Console 3 Software TAS2560 Application software for the TAS2560 part under the Device Control Tab. Below a VBAT level of 2.9 V, the boost will turn on to ensure correct operation but results in increased current consumption. The device is functional until the set brownout level is reached and the device shuts down. The minimum brownout voltage is 2.7 V.
Figure 33. VLIM versus Supply Voltage (VBAT)
When the VBAT voltage drops below the brownout threshold the TAS2560 will power-down to prevent damage. The brownout can be reported on the interrupt pin. See section IRQs and Flags on how to enable this feature. Once the device voltage returns again above the brownout limit the device will need to be externally re-powered, see Brownout.