ZHCS399E August 2011 – January 2017 OMAP-L132
PRODUCTION DATA.
| System Interrupt | Interrupt Name | Source |
|---|---|---|
| 0 | COMMTX | ARM |
| 1 | COMMRX | ARM |
| 2 | NINT | ARM |
| 3 | PRU_EVTOUT0 | PRUSS Interrupt |
| 4 | PRU_EVTOUT1 | PRUSS Interrupt |
| 5 | PRU_EVTOUT2 | PRUSS Interrupt |
| 6 | PRU_EVTOUT3 | PRUSS Interrupt |
| 7 | PRU_EVTOUT4 | PRUSS Interrupt |
| 8 | PRU_EVTOUT5 | PRUSS Interrupt |
| 9 | PRU_EVTOUT6 | PRUSS Interrupt |
| 10 | PRU_EVTOUT7 | PRUSS Interrupt |
| 11 | EDMA3_0_CC0_INT0 | EDMA3_0 Channel Controller 0 Shadow Region 0 Transfer Completion Interrupt |
| 12 | EDMA3_0_CC0_ERRINT | EDMA3_0 Channel Controller 0 Error Interrupt |
| 13 | EDMA3_0_TC0_ERRINT | EDMA3_0 Transfer Controller 0 Error Interrupt |
| 14 | EMIFA_INT | EMIFA |
| 15 | IIC0_INT | I2C0 |
| 16 | MMCSD0_INT0 | MMCSD0 MMC/SD Interrupt |
| 17 | MMCSD0_INT1 | MMCSD0 SDIO Interrupt |
| 18 | PSC0_ALLINT | PSC0 |
| 19 | RTC_IRQS[1:0] | RTC |
| 20 | SPI0_INT | SPI0 |
| 21 | T64P0_TINT12 | Timer64P0 Interrupt 12 |
| 22 | T64P0_TINT34 | Timer64P0 Interrupt 34 |
| 23 | T64P1_TINT12 | Timer64P1 Interrupt 12 |
| 24 | T64P1_TINT34 | Timer64P1 Interrupt 34 |
| 25 | UART0_INT | UART0 |
| 26 | - | Reserved |
| 27 | MPU_BOOTCFG_ERR | Shared MPU and SYSCFG Address/Protection Error Interrupt |
| 28 | SYSCFG_CHIPINT0 | SYSCFG CHIPSIG Register |
| 29 | SYSCFG_CHIPINT1 | SYSCFG CHIPSIG Register |
| 30 | SYSCFG_CHIPINT2 | SYSCFG CHIPSIG Register |
| 31 | SYSCFG_CHIPINT3 | SYSCFG CHIPSIG Register |
| 32 | EDMA3_0_TC1_ERRINT | EDMA3_0 Transfer Controller 1 Error Interrupt |
| 33 | EMAC_C0RXTHRESH | EMAC - Core 0 Receive Threshold Interrupt |
| 34 | EMAC_C0RX | EMAC - Core 0 Receive Interrupt |
| 35 | EMAC_C0TX | EMAC - Core 0 Transmit Interrupt |
| 36 | EMAC_C0MISC | EMAC - Core 0 Miscellaneous Interrupt |
| 37 | EMAC_C1RXTHRESH | EMAC - Core 1 Receive Threshold Interrupt |
| 38 | EMAC_C1RX | EMAC - Core 1 Receive Interrupt |
| 39 | EMAC_C1TX | EMAC - Core 1 Transmit Interrupt |
| 40 | EMAC_C1MISC | EMAC - Core 1 Miscellaneous Interrupt |
| 41 | DDR2_MEMERR | DDR2 Controller |
| 42 | GPIO_B0INT | GPIO Bank 0 Interrupt |
| 43 | GPIO_B1INT | GPIO Bank 1 Interrupt |
| 44 | GPIO_B2INT | GPIO Bank 2 Interrupt |
| 45 | GPIO_B3INT | GPIO Bank 3 Interrupt |
| 46 | GPIO_B4INT | GPIO Bank 4 Interrupt |
| 47 | GPIO_B5INT | GPIO Bank 5 Interrupt |
| 48 | GPIO_B6INT | GPIO Bank 6 Interrupt |
| 49 | GPIO_B7INT | GPIO Bank 7 Interrupt |
| 50 | GPIO_B8INT | GPIO Bank 8 Interrupt |
| 51 | IIC1_INT | I2C1 |
| 52 | - | Reserved |
| 53 | UART_INT1 | UART1 |
| 54 | MCASP_INT | McASP0 Combined RX / TX Interrupts |
| 55 | PSC1_ALLINT | PSC1 |
| 56 | SPI1_INT | SPI1 |
| 57 | - | Reserved |
| 58 | USB0_INT | USB0 Interrupt |
| 59-60 | - | Reserved |
| 61 | UART2_INT | UART2 |
| 62 | - | Reserved |
| 63 | EHRPWM0 | HiResTimer / PWM0 Interrupt |
| 64 | EHRPWM0TZ | HiResTimer / PWM0 Trip Zone Interrupt |
| 65 | EHRPWM1 | HiResTimer / PWM1 Interrupt |
| 66 | EHRPWM1TZ | HiResTimer / PWM1 Trip Zone Interrupt |
| 67 | - | Reserved |
| 68 | T64P2_ALL | Timer64P2 - Combined TINT12 and TINT34 |
| 69 | ECAP0 | ECAP0 |
| 70 | ECAP1 | ECAP1 |
| 71 | ECAP2 | ECAP2 |
| 72 | MMCSD1_INT0 | MMCSD1 MMC/SD Interrupt |
| 73 | MMCSD1_INT1 | MMCSD1 SDIO Interrupt |
| 74 | T64P2_CMPINT0 | Timer64P2 - Compare 0 |
| 75 | T64P2_CMPINT1 | Timer64P2 - Compare 1 |
| 76 | T64P2_CMPINT2 | Timer64P2 - Compare 2 |
| 77 | T64P2_CMPINT3 | Timer64P2 - Compare 3 |
| 78 | T64P2_CMPINT4 | Timer64P2 - Compare 4 |
| 79 | T64P2_CMPINT5 | Timer64P2 - Compare 5 |
| 80 | T64P2_CMPINT6 | Timer64P2 - Compare 6 |
| 81 | T64P2_CMPINT7 | Timer64P2 - Compare 7 |
| 82 | T64P3_CMPINT0 | Timer64P3 - Compare 0 |
| 83 | T64P3_CMPINT1 | Timer64P3 - Compare 1 |
| 84 | T64P3_CMPINT2 | Timer64P3 - Compare 2 |
| 85 | T64P3_CMPINT3 | Timer64P3 - Compare 3 |
| 86 | T64P3_CMPINT4 | Timer64P3 - Compare 4 |
| 87 | T64P3_CMPINT5 | Timer64P3 - Compare 5 |
| 88 | T64P3_CMPINT6 | Timer64P3 - Compare 6 |
| 89 | T64P3_CMPINT7 | Timer64P3 - Compare 7 |
| 90 | ARMCLKSTOPREQ | PSC0 |
| 91-92 | - | Reserved |
| 93 | EDMA3_1_CC0_INT0 | EDMA3_1 Channel Controller 0 Shadow Region 0 Transfer Completion Interrupt |
| 94 | EDMA3_1_CC0_ERRINT | EDMA3_1Channel Controller 0 Error Interrupt |
| 95 | EDMA3_1_TC0_ERRINT | EDMA3_1 Transfer Controller 0 Error Interrupt |
| 96 | T64P3_ALL | Timer64P 3 - Combined TINT12 and TINT34 |
| 97 | MCBSP0_RINT | McBSP0 Receive Interrupt |
| 98 | MCBSP0_XINT | McBSP0 Transmit Interrupt |
| 99 | MCBSP1_RINT | McBSP1 Receive Interrupt |
| 100 | MCBSP1_XINT | McBSP1 Transmit Interrupt |