ZHCS399E August 2011 – January 2017 OMAP-L132
PRODUCTION DATA.
The minimum stackup required for routing the device is a six layer stack as shown in Table 6-28. Additional layers may be added to the PCB stack up to accommodate other circuitry or to reduce the size of the PCB footprint.Complete stack up specifications are provided in Table 6-29.
| LAYER | TYPE | DESCRIPTION |
|---|---|---|
| 1 | Signal | Top Routing Mostly Horizontal |
| 2 | Plane | Ground |
| 3 | Plane | Power |
| 4 | Signal | Internal Routing |
| 5 | Plane | Ground |
| 6 | Signal | Bottom Routing Mostly Vertical |
| NO. | PARAMETER | MIN | TYP | MAX | UNIT |
|---|---|---|---|---|---|
| 1 | PCB Routing/Plane Layers | 6 | |||
| 2 | Signal Routing Layers | 3 | |||
| 3 | Full ground layers under DDR2/mDDR routing region | 2 | |||
| 4 | Number of ground plane cuts allowed within DDR routing region | 0 | |||
| 5 | Number of ground reference planes required for each DDR2/mDDR routing layer | 1 | |||
| 6 | Number of layers between DDR2/mDDR routing layer and reference ground plane | 0 | |||
| 7 | PCB Routing Feature Size | 4 | Mils | ||
| 8 | PCB Trace Width w | 4 | Mils | ||
| 8 | PCB BGA escape via pad size | 18 | Mils | ||
| 9 | PCB BGA escape via hole size | 8 | Mils | ||
| 10 | Device BGA pad size(1) | ||||
| 11 | DDR2/mDDR Device BGA pad size(2) | ||||
| 12 | Single Ended Impedance, Zo | 50 | 75 | Ω | |
| 13 | Impedance Control(3) | Z-5 | Z | Z+5 | Ω |