ZHCS399E August 2011 – January 2017 OMAP-L132
PRODUCTION DATA.
| NO. | PARAMETER | 1.2V, 1.1V | 1.0V | UNIT | |||
|---|---|---|---|---|---|---|---|
| MIN | MAX | MIN | MAX | ||||
| 1 | td(MII_TXCLKH-MTXD) | Delay time, MII_TXCLK high to transmit selected signals valid | 2 | 25 | 2 | 32 | ns |
Figure 6-49 EMAC Transmit Interface Timing
| NO. | 1.2V, 1.1V(1) | UNIT | ||||
|---|---|---|---|---|---|---|
| MIN | TYP | MAX | ||||
| 1 | tc(REFCLK) | Cycle Time, RMII_MHZ_50_CLK | 20 | ns | ||
| 2 | tw(REFCLKH) | Pulse Width, RMII_MHZ_50_CLK High | 7 | 13 | ns | |
| 3 | tw(REFCLKL) | Pulse Width, RMII_MHZ_50_CLK Low | 7 | 13 | ns | |
| 6 | tsu(RXD-REFCLK) | Input Setup Time, RXD Valid before RMII_MHZ_50_CLK High | 4 | ns | ||
| 7 | th(REFCLK-RXD) | Input Hold Time, RXD Valid after RMII_MHZ_50_CLK High | 2 | ns | ||
| 8 | tsu(CRSDV-REFCLK) | Input Setup Time, CRSDV Valid before RMII_MHZ_50_CLK High | 4 | ns | ||
| 9 | th(REFCLK-CRSDV) | Input Hold Time, CRSDV Valid after RMII_MHZ_50_CLK High | 2 | ns | ||
| 10 | tsu(RXER-REFCLK) | Input Setup Time, RXER Valid before RMII_MHZ_50_CLK High | 4 | ns | ||
| 11 | th(REFCLKR-RXER) | Input Hold Time, RXER Valid after RMII_MHZ_50_CLK High | 2 | ns | ||
Note: Per the RMII industry specification, the RMII reference clock (RMII_MHZ_50_CLK) must have jitter tolerance of 50 ppm or less.
| NO. | PARAMETER | 1.2V, 1.1V(1) | UNIT | |||
|---|---|---|---|---|---|---|
| MIN | TYP | MAX | ||||
| 4 | td(REFCLK-TXD) | Output Delay Time, RMII_MHZ_50_CLK High to TXD Valid | 2.5 | 13 | ns | |
| 5 | td(REFCLK-TXEN) | Output Delay Time, RMII_MHZ_50_CLK High to TXEN Valid | 2.5 | 13 | ns | |
Figure 6-50 RMII Timing Diagram