ZHCS399E August 2011 – January 2017 OMAP-L132
PRODUCTION DATA.
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
Table 6-33 lists the clock net classes for the DDR2/mDDR interface. Table 6-34 lists the signal net classes, and associated clock net classes, for the signals in the DDR2/mDDR interface. These net classes are used for the termination and routing rules that follow.
| CLOCK NET CLASS | Soc PIN NAMES |
|---|---|
| CK | DDR_CLKP / DDR_CLKN |
| DQS0 | DDR_DQS[0] |
| DQS1 | DDR_DQS[1] |
| SIGNAL NET CLASS | ASSOCIATED CLOCK NET CLASS | Soc PIN NAMES |
|---|---|---|
| ADDR_CTRL | CK | DDR_BA[2:0], DDR_A[13:0], DDR_CS, DDR_CAS, DDR_RAS, DDR_WE, DDR_CKE |
| D0 | DQS0 | DDR_D[7:0], DDR_DQM0 |
| D1 | DQS1 | DDR_D[15:8], DDR_DQM1 |
| DQGATE | CK, DQS0, DQS1 | DDR_DQGATE0, DDR_DQGATE1 |