ZHCSLM0A May 2020 – January 2021 LMK5B12204
PRODUCTION DATA
APLL1 has a 24-bit (programmable) or40-bit (fixed) fractional-N divider and APLL2 has a 24-bit (programmable) fractional-N divider to support high-resolution frequency synthesis and very low phase noise and jitter. APLL1 has the ability to tune its VCO1 frequency through sigma-delta modulator (SDM) control in DPLL mode. APLL2 has the ability to lock its VCO2 frequency to the VCO1 frequency.
In free-run mode, APLL1 uses the XO input as an initial reference clock to VCO1. The PFD of the APLL1 compares the fractional-N divided clock with its reference clock and generates a control signal. The control signal is filtered by the APLL1 loop filter to generate the control voltage of the VCO1 to set its output frequency. The SDM modulates the N divider ratio to get the desired fractional ratio between the PFD input and the VCO output. APLL2 operates similar to APLL1, but the user can select the reference of the APLL2 from either the VCO1 clock or XO clock.
In DPLL mode, the APLL1 fractional SDM is controlled by the DPLL loop to pull the VCO1 frequency into lock with the DPLL reference input. If APLL2 derives its reference from VCO1, then VCO2 will be effectively locked to the DPLL reference input, assuming there is no synthesis error introduced by the fractional N divide ratio of APLL2.