ZHCSLM0A May 2020 – January 2021 LMK5B12204
PRODUCTION DATA
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 Revision History
- 5 說明（續(xù)）
- 6 Pin Configuration and Functions
- 7 Specifications
- 8 Parameter Measurement Information
-
9 Detailed Description
- 9.1 Overview
- 9.2 Functional Block Diagram
- 9.3
Feature Description
- 9.3.1 Oscillator Input (XO_P/N)
- 9.3.2 Reference Inputs (PRIREF_P/N and SECREF_P/N)
- 9.3.3 Clock Input Interfacing and Termination
- 9.3.4 Reference Input Mux Selection
- 9.3.5 Hitless Switching
- 9.3.6 Gapped Clock Support on Reference Inputs
- 9.3.7 Input Clock and PLL Monitoring, Status, and Interrupts
- 9.3.8
PLL Relationships
- 9.3.8.1 PLL Frequency Relationships
- 9.3.8.2 Analog PLLs (APLL1, APLL2)
- 9.3.8.3 APLL Reference Paths
- 9.3.8.4 APLL Phase Frequency Detector (PFD) and Charge Pump
- 9.3.8.5 APLL Feedback Divider Paths
- 9.3.8.6 APLL Loop Filters (LF1, LF2)
- 9.3.8.7 APLL Voltage Controlled Oscillators (VCO1, VCO2)
- 9.3.8.8 APLL VCO Clock Distribution Paths (P1, P2)
- 9.3.8.9 DPLL Reference (R) Divider Paths
- 9.3.8.10 DPLL Time-to-Digital Converter (TDC)
- 9.3.8.11 DPLL Loop Filter (DLF)
- 9.3.8.12 DPLL Feedback (FB) Divider Path
- 9.3.9 Output Clock Distribution
- 9.3.10 Output Channel Muxes
- 9.3.11 Output Dividers (OD)
- 9.3.12 Clock Outputs (OUTx_P/N)
- 9.3.13 Glitchless Output Clock Start-Up
- 9.3.14 Clock Output Interfacing and Termination
- 9.3.15 Output Synchronization (SYNC)
- 9.4 Device Functional Modes
- 9.5 Programming
- 10Application and Implementation
- 11Power Supply Recommendations
- 12Layout
- 13Device and Documentation Support
- 14Mechanical, Packaging, and Orderable Information
封裝選項
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RGZ|48
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RGZ|48
訂購信息
9.3.7.6 Interrupt
Any of the two status pins can be configured as a device interrupt output pin. The interrupt logic configuration is set through registers. When the interrupt logic is enabled, the interrupt output can be triggered from any combination of interrupt status indicators, including LOS for the XO, LOR for the selected DPLL input, LOL for each APLL and the DPLL, and holdover and switchover events for the DPLL. When the interrupt polarity is set high, a rising edge on the live status bit will assert its interrupt flag (sticky bit). Otherwise, when the polarity is set low, a falling edge on the live status bit will assert its interrupt flag. Any individual interrupt flag can be masked so it does not trigger the interrupt output. The unmasked interrupt flags are combined by the AND/ OR gate to generate the interrupt output, which can be selected on either status pin.
When a system host detects an interrupt from the LMK5B12204, the host can read the interrupt flag or "sticky" registers to identify which bits were asserted to resolve the fault conditions in the system. After the system faults have been resolved, the host can clear the interrupt output by writing zeros to the sticky bits that were asserted.
Figure 9-21 Status and Interrupt