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ZHCSLM0A May 2020 – January 2021 LMK5B12204

PRODUCTION DATA

封裝選項

機械數據 (封裝 | 引腳)

RGZ|48
- MPQF123F

散熱焊盤機械數據 (封裝 | 引腳)

RGZ|48
- QFND031W

訂購信息

6.1 Device Start-Up Modes

The HW_SW_CTRL input pin selects the device start-up mode that determines the memory page (EEPROM or ROM) used to initialize the registers, the serial interface, and the logic pin functions at power-on reset. The initial register settings determine the frequency configuration of the device on start-up. After start-up, the device registers can be accessed through the serial interface for device monitoring and programming, and the logic pins will function as defined by the selected mode.

Table 6-2 Device Start-Up Modes

HW_SW_CTRL INPUT LEVEL⁽¹⁾	START-UP MODE	MODE DESCRIPTION
0	EEPROM + I²C (Soft pin mode)	Registers are initialized from EEPROM, and I²C interface is enabled. Logic pins: SDA/SDI, SCL/SCK: I²C Data, I²C Clock (open-drain) GPIO0/SYNCN: Output SYNC Input (active low). Pull up externally if not used. GPIO1/SCS⁽¹⁾: I²C Address LSB Select (Low = 00b, Float = 01b, High = 10b) GPIO2/SDO/FINC⁽²⁾: DPLL DCO Frequency Increment (active high) STATUS1/FDEC⁽²⁾: DPLL DCO Frequency Decrement (active high), or Status output
Float (V_IM)	EEPROM + SPI (Soft pin mode)	Registers are initialized from EEPROM, and SPI interface is enabled. Logic pins: SDA/SDI, SCL/SCK: SPI Data In (SDI), SPI Clock (SCK) GPIO0/SYNCN: Output SYNC Input (active low). Pull up externally if not used. GPIO1/SCS: SPI Chip Select (SCS) GPIO2/SDO/FINC: SPI Data Out (SDO)
1	ROM + I²C (Hard pin mode)	Registers are initialized from the ROM page selected by GPIO pins, and I²C interface is enabled. Logic pins: SDA/SDI, SCL/SCK: I²C Data, I²C Clock (open-drain) GPIO[2:0] ⁽¹⁾: ROM Page Select Inputs (000b to 111b) during POR. After POR, GPIO2/SDO/FINC and STATUS1/FDEC pins can function the same as for HW_SW_CTRL = 0.

(1) The input levels on these pins are sampled only during POR.

(2) FINC and FDEC pins are only available when DCO mode and GPIO pin control are enabled by registers.

Note:

To ensure proper start-up into EEPROM + SPI Mode, the HW_SW_CTRL, STATUS0, and STATUS1 pins must all be floating or biased to V_IM (0.8-V typical) before the PDN pin is pulled high. These three pins momentarily operate as 3-level inputs and get sampled at the low-to-high transition of PDN to determine the device start-up mode during POR. If any of these pins are connected to a system host (MCU or FPGA), TI recommends using external biasing resistors on each pin (10-kΩ pullup to 3.3 V with 3.3-kΩ pulldown to GND) to set the inputs to V_IM during POR. After power up, the STATUS pins can operate as LVCMOS outputs to overdrive the external resistor bias for normal status operation.