ZHCSLM0A May 2020 – January 2021 LMK5B12204
PRODUCTION DATA
The reference amplitude detector determines if the input meets the amplitude-related threshold depending on the input buffer configuration. For differential input mode, the amplitude detector clears its LOR_AMP flag when the differential input voltage swing (peak-to-peak) is greater than the minimum threshold selected by the registers (400, 500, or 600 mVpp nominal). For LVCMOS input mode, the input slew rate detector clears its LOR_AMP flag when its slew rate is faster than 0.2 V/ns on the clock edge selected by the registers (rising edge, falling edge, or both edges). If either the differential or LVCMOS input clock does not meet the specified thresholds, the amplitude detector will set the LOR_AMP flag and disqualify the input.
If the input frequency is below 5 MHz, the differential input detector may signal a false flag. In this case, the amplitude detector should be disabled and at least one other input monitor (frequency, window, or 1-PPS phase valid detector) should be enabled to validate the input clock. The LVCMOS input detector can be used for low-frequency clocks down to 1 Hz or 1 PPS.