The following equations provide the PLL frequency relationships required to achieve closed-loop operation according to the selected PLL mode. The TICS Pro programming software can be used to generate valid divider settings based on the desired frequency plan configuration and PLL mode.
- To operate APLL1 in Free-run mode (locked to the XO input), the conditions in Equation 1 and Equation 2 must be met.
- To operate APLL1 in DPLL mode, the conditions in Equation 1, Equation 2, Equation 3, and Equation 4 must be met.
- To operate APLL2 in Cascaded mode, the conditions in Equation 1, Equation 2, Equation 5, and Equation 7 must be met.
- To operate APLL2 in Non-cascaded mode, the conditions in Equation 6 and Equation 7 must be met.
Note that any divider in the following equations refer to the actual divide value (or range) and not its programmable register value.
Equation 1 and Equation 2 relate to APLL1:
Equation 1. fPD1 = fXO × DXO / RXO
where
- fPD1 = APLL1 phase detector frequency
- fXO: XO input frequency
- DXO: XO input doubler (1 = disabled, 2 = enabled)
- RXO: APLL1 XO Input R divider value (1 to 32)
Equation 2. fVCO1 = fPD1 × (INTAPLL1 + NUMAPLL1 / DENAPLL1)
where
- fVCO1: VCO1 frequency
- INTAPLL1: APLL1 N divider integer value (12 bits, 1 to 212 – 1)
- NUMAPLL1: APLL1 N divider numerator value (40 bits, 0 to 240 – 1)
- DENAPLL1: APLL1 N divider denominator value (fixed 240 or programmable 1 to 224-1)
- 0.0625 < NUMAPLL1 / DENAPLL1 < 0.9375 (In DPLL Mode)
Equation 3 and Equation 4 relate to the DPLL:
Equation 3. fTDC = fPRIREF / RPRIREF = fSECREF / RSECREF
where
- fTDC: DPLL TDC input frequency (see Equation 3)
- fPRIREF or fSECREF: PRIREF or SECREF input frequency
- RPRIREF or RSECREF: PRIREF or SECREF R divider value (16 bits, 1 to 216 – 1)
Equation 4. fVCO1 = fTDC × 2 × PRDPLL × (INTDPLL + NUMDPLL/ DENDPLL)
where
- PRDPLL: DPLL prescaler divider value (2 to 17)
- INTDPLL: DPLL FB divider integer value (30 bits, 1 to 230 – 1)
- NUMDPLL: DPLL FB divider numerator value (40 bits, 0 to 240 – 1)
- DENDPLL: DPLL FB divider denominator value (40 bits, 1 to 240)
Equation 5, Equation 6, and Equation 7 relate to APLL2:
Equation 5. Cascaded APLL2: fPD2 = fVCO1 / (RAPLL2_PRE × RAPLL2_SEC)
where
- fPD2: APLL2 phase detector frequency
- RAPLL2_PRE: Cascaded APLL2 Pre R divider value (3 to 6)
- RAPLL2_SEC: Cascaded APLL2 Secondary R divider value (1 to 32)
Equation 6. Non-Cascaded APLL2: fPD2 = fXO × DXO
Equation 7. fVCO2 = fPD2 × (INTAPLL2 + NUMAPLL2 / DENAPLL2)
where
- fVCO2: VCO2 frequency
- INTAPLL2: APLL2 N divider integer value (9 bits, 1 to 29 – 1)
- NUMAPLL2: APLL2 N divider numerator value (24 bits, 0 to 224 – 1)
- DENAPLL2: APLL2 N divider denominator value (fixed 224 or programmable 1 to 224-1.)
Equation 8, Equation 9, Equation 10, and Equation 11 relate to the output frequency, which depends on the selected APLL clock source and output divider value:
Equation 8. APLL1 selected: fCHxMUX = fVCO1
Equation 9. APLL2 selected: fCHxMUX = fVCO2 / PnAPLL2
Equation 10. OUT[0:3]: fOUTx = fCHxMUX / ODOUTx
Equation 11.
where
- fCHxMUX: Output mux source frequency (APLL1 or APLL2 post-divider clock)
- PnAPLL2: APLL2 primary "P1" or secondary "P2" post-divide value (2 to 7)
- fOUTx: Output clock frequency (x = 0 to 7)
- ODOUTx: OUTx output divider value (8 bits, 1 to 28)