ZHCSLM0A May 2020 – January 2021 LMK5B12204
PRODUCTION DATA
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 Revision History
- 5 說明（續(xù)）
- 6 Pin Configuration and Functions
- 7 Specifications
- 8 Parameter Measurement Information
-
9 Detailed Description
- 9.1 Overview
- 9.2 Functional Block Diagram
- 9.3
Feature Description
- 9.3.1 Oscillator Input (XO_P/N)
- 9.3.2 Reference Inputs (PRIREF_P/N and SECREF_P/N)
- 9.3.3 Clock Input Interfacing and Termination
- 9.3.4 Reference Input Mux Selection
- 9.3.5 Hitless Switching
- 9.3.6 Gapped Clock Support on Reference Inputs
- 9.3.7 Input Clock and PLL Monitoring, Status, and Interrupts
- 9.3.8
PLL Relationships
- 9.3.8.1 PLL Frequency Relationships
- 9.3.8.2 Analog PLLs (APLL1, APLL2)
- 9.3.8.3 APLL Reference Paths
- 9.3.8.4 APLL Phase Frequency Detector (PFD) and Charge Pump
- 9.3.8.5 APLL Feedback Divider Paths
- 9.3.8.6 APLL Loop Filters (LF1, LF2)
- 9.3.8.7 APLL Voltage Controlled Oscillators (VCO1, VCO2)
- 9.3.8.8 APLL VCO Clock Distribution Paths (P1, P2)
- 9.3.8.9 DPLL Reference (R) Divider Paths
- 9.3.8.10 DPLL Time-to-Digital Converter (TDC)
- 9.3.8.11 DPLL Loop Filter (DLF)
- 9.3.8.12 DPLL Feedback (FB) Divider Path
- 9.3.9 Output Clock Distribution
- 9.3.10 Output Channel Muxes
- 9.3.11 Output Dividers (OD)
- 9.3.12 Clock Outputs (OUTx_P/N)
- 9.3.13 Glitchless Output Clock Start-Up
- 9.3.14 Clock Output Interfacing and Termination
- 9.3.15 Output Synchronization (SYNC)
- 9.4 Device Functional Modes
- 9.5 Programming
- 10Application and Implementation
- 11Power Supply Recommendations
- 12Layout
- 13Device and Documentation Support
- 14Mechanical, Packaging, and Orderable Information
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RGZ|48
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RGZ|48
訂購信息
9.2.2 DPLL Mode
In DPLL mode, the external XO input source determines the free-run and holdover frequency stability and accuracy of the output clocks. The BAW VCO1 determines the APLL1 output clock phase noise and jitter performance over the 12-kHz to 20-MHz integration band, regardless of the frequency and jitter of the XO input. This allows the use a cost-effective, low-frequency TCXO or OCXO as the external XO input to support standards-compliant frequency stability and low loop bandwidth (≤10 Hz) required in synchronization applications like SyncE and IEEE 1588.
The principle of operation for DPLL mode after power-on reset and initialization is as follows. If APLL2 is in Cascaded mode as shown in Figure 9-3, VCO1 is held at the nominal center frequency of 2.5 GHz while APLL2 locks. Then APLL1 locks the VCO1 frequency to the external XO input and operates in free-run mode. Once a valid DPLL reference input is detected, the DPLL begins lock acquisition. The DPLL TDC compares the phase of the selected reference input clock and the FB divider clock (from VCO1) and generates a digital correction word corresponding to the phase error. The correction word is filtered by the DLF, and the DLF output controls the APLL1 N divider SDM to pull the VCO1 frequency into lock with the reference input. VCO2 will track the VCO1 domain during DPLL lock acquisition and locked modes, allowing the user to synchronize the clock domain of the APLL2 to the DPLL reference input. Cascading APLL2 provides a high-frequency, ultra-low-jitter reference clock from VCO1 to minimize the APLL2 in-band phase noise/jitter impact that would otherwise occur if the reference of the APLL2 is from a XO/TCXO/OCXO with low frequency and/or high phase noise floor.
If APLL2 is not cascaded as shown in Figure 9-4, VCO2 will lock to the XO input after initialization and operate independently of the DPLL/APLL1 domain.
When all reference inputs to the DPLL are lost, the PLLs will enter holdover mode and track the stability and accuracy of the external XO source.
If DCO mode is enabled on the DPLL, a frequency deviation step value (FDEV) can be programmed and used to adjust (increment or decrement) the FB divider SDM of the DPLL, where the frequency adjustment effectively propagates through the APLL1 domain (and APLL2 domain if cascaded) to the output clocks.
The programmed DPLL loop bandwidth (BWDPLL) should be lower than all of the following:
- 1/100th of the DPLL TDC rate
- the APLL1 loop bandwidth (1 to 10 kHz typical)
- the maximum DPLL bandwidth setting of 4 kHz.
Figure 9-3 DPLL Mode With Cascaded APLL2
Figure 9-4 DPLL Mode With Non-Cascaded APLL2