ZHCSLM0A May 2020 – January 2021 LMK5B12204
PRODUCTION DATA
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 Revision History
- 5 說明（續(xù)）
- 6 Pin Configuration and Functions
- 7 Specifications
- 8 Parameter Measurement Information
-
9 Detailed Description
- 9.1 Overview
- 9.2 Functional Block Diagram
- 9.3
Feature Description
- 9.3.1 Oscillator Input (XO_P/N)
- 9.3.2 Reference Inputs (PRIREF_P/N and SECREF_P/N)
- 9.3.3 Clock Input Interfacing and Termination
- 9.3.4 Reference Input Mux Selection
- 9.3.5 Hitless Switching
- 9.3.6 Gapped Clock Support on Reference Inputs
- 9.3.7 Input Clock and PLL Monitoring, Status, and Interrupts
- 9.3.8
PLL Relationships
- 9.3.8.1 PLL Frequency Relationships
- 9.3.8.2 Analog PLLs (APLL1, APLL2)
- 9.3.8.3 APLL Reference Paths
- 9.3.8.4 APLL Phase Frequency Detector (PFD) and Charge Pump
- 9.3.8.5 APLL Feedback Divider Paths
- 9.3.8.6 APLL Loop Filters (LF1, LF2)
- 9.3.8.7 APLL Voltage Controlled Oscillators (VCO1, VCO2)
- 9.3.8.8 APLL VCO Clock Distribution Paths (P1, P2)
- 9.3.8.9 DPLL Reference (R) Divider Paths
- 9.3.8.10 DPLL Time-to-Digital Converter (TDC)
- 9.3.8.11 DPLL Loop Filter (DLF)
- 9.3.8.12 DPLL Feedback (FB) Divider Path
- 9.3.9 Output Clock Distribution
- 9.3.10 Output Channel Muxes
- 9.3.11 Output Dividers (OD)
- 9.3.12 Clock Outputs (OUTx_P/N)
- 9.3.13 Glitchless Output Clock Start-Up
- 9.3.14 Clock Output Interfacing and Termination
- 9.3.15 Output Synchronization (SYNC)
- 9.4 Device Functional Modes
- 9.5 Programming
- 10Application and Implementation
- 11Power Supply Recommendations
- 12Layout
- 13Device and Documentation Support
- 14Mechanical, Packaging, and Orderable Information
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RGZ|48
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RGZ|48
訂購信息
9.3.7.4 Tuning Word History
The DPLL domain has a tuning word history monitor block that determines the initial output frequency accuracy upon entry into holdover. The tuning word can be updated from one of three sources depending on the DPLL operating mode:
- Locked Mode: From the output of the digital loop filter when locked
- Holdover Mode: From the final output of the history monitor
- Free Run Mode: From the free-run tuning word register (user defined)
When the history monitor is enabled and the DPLL is locked, it effectively averages the reference input frequency by accumulating history from the digital loop filter output during a programmable averaging time (TAVG). Once the input becomes invalid, the final tuning word value is stored to determine the initial holdover frequency accuracy. Generally, a longer TAVG time will produce a more accurate initial holdover frequency. The stability of the 0-ppm reference clock (XO input) determines the long-term stability and accuracy of the holdover output frequency.
There is also a separate programmable delay timer (TIGN) that can be set to ignore the history data that is corrupted just prior to entry into holdover. The history data could be corrupted if a tuning word update occurs while the input clock is failing and before it is detected by the input monitors. Both TAVG and TIGN times are programmable through the HISTCNT and HISTDLY register bits, respectively, and are related to the TDC rate.
The tuning word history is initially cleared after a device hard-reset or soft-reset. After the DPLL locks to a new reference, the history monitor waits for the first TAVG timer to expire before storing the first tuning word value and begins to accumulate history. The history monitor will not clear the previous history value during reference switchover or holdover exit. The history can be manually cleared or reset by toggling the history enable bit (HIST_EN = 1 → 0 → 1), if needed.
If the TAVG period is set very long (minutes or hours) to obtain a more precise historical average frequency, it is possible for a switchover or holdover event to occur before the first tuning word is stored and available for use. To overcome this, there is an intermediate history update option (HIST_INTMD). If the history is reset, then the intermediate average can be updated at intervals of TAVG/2K , where K = HIST_INTMD to 0, during the first TAVG period only. If HIST_INTMD = 0, there is no intermediate update and the first average is stored after the first TAVG period. However, if HIST_INTMD = 4, then four intermediate averages are taken at TAVG/16, TAVG/8, TAVG/4, and TAVG/2, as well as at TAVG. After the first TAVG period, all subsequent history updates occur at the TAVG period.
When no tuning word history exists, the free-run tuning word value (TUNING_FREE_RUN) determines the initial holdover output frequency accuracy.