ZHCSLM0A May 2020 – January 2021 LMK5B12204
PRODUCTION DATA
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 Revision History
- 5 說明（續(xù)）
- 6 Pin Configuration and Functions
- 7 Specifications
- 8 Parameter Measurement Information
-
9 Detailed Description
- 9.1 Overview
- 9.2 Functional Block Diagram
- 9.3
Feature Description
- 9.3.1 Oscillator Input (XO_P/N)
- 9.3.2 Reference Inputs (PRIREF_P/N and SECREF_P/N)
- 9.3.3 Clock Input Interfacing and Termination
- 9.3.4 Reference Input Mux Selection
- 9.3.5 Hitless Switching
- 9.3.6 Gapped Clock Support on Reference Inputs
- 9.3.7 Input Clock and PLL Monitoring, Status, and Interrupts
- 9.3.8
PLL Relationships
- 9.3.8.1 PLL Frequency Relationships
- 9.3.8.2 Analog PLLs (APLL1, APLL2)
- 9.3.8.3 APLL Reference Paths
- 9.3.8.4 APLL Phase Frequency Detector (PFD) and Charge Pump
- 9.3.8.5 APLL Feedback Divider Paths
- 9.3.8.6 APLL Loop Filters (LF1, LF2)
- 9.3.8.7 APLL Voltage Controlled Oscillators (VCO1, VCO2)
- 9.3.8.8 APLL VCO Clock Distribution Paths (P1, P2)
- 9.3.8.9 DPLL Reference (R) Divider Paths
- 9.3.8.10 DPLL Time-to-Digital Converter (TDC)
- 9.3.8.11 DPLL Loop Filter (DLF)
- 9.3.8.12 DPLL Feedback (FB) Divider Path
- 9.3.9 Output Clock Distribution
- 9.3.10 Output Channel Muxes
- 9.3.11 Output Dividers (OD)
- 9.3.12 Clock Outputs (OUTx_P/N)
- 9.3.13 Glitchless Output Clock Start-Up
- 9.3.14 Clock Output Interfacing and Termination
- 9.3.15 Output Synchronization (SYNC)
- 9.4 Device Functional Modes
- 9.5 Programming
- 10Application and Implementation
- 11Power Supply Recommendations
- 12Layout
- 13Device and Documentation Support
- 14Mechanical, Packaging, and Orderable Information
封裝選項
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RGZ|48
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RGZ|48
訂購信息
9.2.1 PLL Architecture Overview
Figure 9-2 shows the PLL architecture implemented in the LMK5B12204. The primary "PLL1" channel consists of a digital PLL (DPLL) and analog PLL (APLL1) with integrated BAW VCO (VCO1) capable of generating clocks with RMS phase jitter of 50-fs typical. A secondary APLL (APLL2) with integrated LC VCO (VCO2) can be used as an additional clock generation domain with RMS phase jitter of 130-fs typical.
The DPLL is comprised of a time-to-digital converter (TDC), digital loop filter (DLF), and 40-bit fractional feedback (FB) divider with sigma-delta-modulator (SDM). The APLLs are comprised of a reference (R) divider, phase-frequency detector (PFD), loop filter (LF), fractional feedback (N) divider with SDM, and VCO. APLL2 has a reference selection mux that allows APLL2 to be either locked to the VCO domain of the APLL1 (Cascaded APLL2) or locked to the XO input (Non-Cascaded APLL2). Otherwise, APLL2 can be disabled (powered-down) if this clock domain is not needed. The VCO of the APLL1 feeds the output clock distribution blocks directly, whereas the VCO of the APLL2 drives the clock distribution blocks through the VCO post-dividers.
The following sections describe the basic principle of operation for DPLL mode and APLL-only mode. See Section 9.4.2 for more details on the PLL modes of operation including holdover.