ZHCSN08D August 2020 – April 2024 DRV8714-Q1 , DRV8718-Q1
PRODMIX
- 1
- 1 特性
- 2 應(yīng)用
- 3 說(shuō)明
- 4 Device Comparison Table
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 External Components
- 7.3.2 Device Interface Variants
- 7.3.3 Input PWM Control Modes
- 7.3.4 Smart Gate Driver
- 7.3.5 Tripler (Dual-Stage) Charge Pump
- 7.3.6 Wide Common-Mode Current Shunt Amplifiers
- 7.3.7 Pin Diagrams
- 7.3.8
Protection and Diagnostics
- 7.3.8.1 Gate Driver Disable (DRVOFF/nFLT and EN_DRV)
- 7.3.8.2 Low IQ Powered Off Braking (POB, BRAKE)
- 7.3.8.3 Fault Reset (CLR_FLT)
- 7.3.8.4 DVDD Logic Supply Power on Reset (DVDD_POR)
- 7.3.8.5 PVDD Supply Undervoltage Monitor (PVDD_UV)
- 7.3.8.6 PVDD Supply Overvoltage Monitor (PVDD_OV)
- 7.3.8.7 VCP Charge Pump Undervoltage Lockout (VCP_UV)
- 7.3.8.8 MOSFET VDS Overcurrent Protection (VDS_OCP)
- 7.3.8.9 Gate Driver Fault (VGS_GDF)
- 7.3.8.10 Thermal Warning (OTW)
- 7.3.8.11 Thermal Shutdown (OTSD)
- 7.3.8.12 Offline Short Circuit and Open Load Detection (OOL and OSC)
- 7.3.8.13 Watchdog Timer
- 7.3.8.14 Fault Detection and Response Summary Table
- 7.4 Device Functional Modes
- 7.5 Programming
- 8 Register Maps
- 9 Application Implementation
- 10Device Documentation and Support
- 11Revision History
- 12Mechanical, Packaging, and Orderable Information
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
訂購(gòu)信息
7.3.3.2.1 DRV8714-Q1 H-Bridge Control
In the H-bridge control mode, each two pairs of half-bridge gate drivers can be controlled as an H-bridge gate driver for a total of two H-bridge gate drivers for the DRV8714-Q1. The H-bridge pairs are half-bridges 1 / 2 and 3 / 4 for the DRV8714-Q1. The DRV8714-Q1 can control the 2 H-bridge gate driver pairs through direct inputs pins or SPI control registers. The H-bridge gate drivers have two input control modes that can be configured through the BRG_MODE register setting (01b = PH/EN and 10b = PWM) on SPI interface variants or the MODE pin (Level 2 = PH/EN and Level 3 = PWM) on H/W interface variants. The PH/EN mode allows for the H-bridge to be controlled with a speed/direction type of interface commanded by one PWM signal and one GPIO signal. The PWM mode allows for the H-bridge to be controlled with a more advanced scheme typically requiring two PWM signals. This allows the H-bridge driver to enter four different output states for additional control flexibility if required.
The DRV8714-Q1 PWM inputs pins (IN1/EN1, IN2/PH1, IN3/EN2, IN4/PH2) are used to set the PWM frequency and duty cycle for the assigned output. If PWM control is not required, the two h-bridge gate drivers can be controlled directly through the SPI control registers. The INx/ENx and INx/PHx SPI control can be enabled through the INx/ENx_MODE and INx/PHx_MODE register settings. Each H-bridge can be individually set to Hi-Z through the HIZ register setting.
The default active freewheeling mode is active low-side. The DRV8714-Q1 SPI interface variants provide the ability to configure the freewheeling state through the FW register setting. This setting can be utilized to modify the bridge between low-side or high-side active freewheeling. The H/W interface variants default to low-side freewheeling.
The PH/EN control logic and output states for the gate drivers are shown in Table 7-9 and Table 7-10.
| INPUT | OUTPUT | |||||||||
|---|---|---|---|---|---|---|---|---|---|---|
| IN1/EN1 | IN2/PH1 | FW1 | HIZ1 | GH1 | GL1 | GH2 | GL2 | SH1 | SH2 | DESCRIPTION |
| 0 | X | 0b | 0 | L | H | L | H | L | L | Low-Side Active Freewheel |
| 0 | X | 1b | 0 | H | L | H | L | H | H | High-Side Active Freewheel |
| 1 | 0 | X | 0 | L | H | H | L | L | H | Drive SH2 → SH1 (Reverse) |
| 1 | 1 | X | 0 | H | L | L | H | H | L | Drive SH1 → SH2 (Forward) |
| X | X | X | 1 | L | L | L | L | HI-Z | HI-Z | High-Impedance |
| INPUT | OUTPUT | |||||||||
|---|---|---|---|---|---|---|---|---|---|---|
| IN3/EN2 | IN4/PH2 | FW2 | HIZ2 | GH3 | GL3 | GH4 | GL4 | SH3 | SH4 | DESCRIPTION |
| 0 | X | 0b | 0 | L | H | L | H | L | L | Low-Side Active Freewheel |
| 0 | X | 1b | 0 | H | L | H | L | H | H | High-Side Active Freewheel |
| 1 | 0 | X | 0 | L | H | H | L | L | H | Drive SH4 → SH3 (Reverse) |
| 1 | 1 | X | 0 | H | L | L | H | H | L | Drive SH3 → SH4 (Forward) |
| X | X | X | 1 | L | L | L | L | HI-Z | HI-Z | High-Impedance |
The PWM control logic and output states for the gate drivers are shown in Table 7-11 and Table 7-12
| INPUT | OUTPUT | |||||||||
|---|---|---|---|---|---|---|---|---|---|---|
| IN1/EN1 | IN2/PH1 | FW1 | HIZ1 | GH1 | GL1 | GH2 | GL2 | SH1 | SH2 | DESCRIPTION |
| 0 | 0 | X | 0 | L | L | L | L | HI-Z | HI-Z | Diode Freewheel (Coast) |
| 0 | 1 | X | 0 | L | H | H | L | L | H | Drive SH2 → SH1 (Reverse) |
| 1 | 0 | X | 0 | H | L | L | H | H | L | Drive SH1 → SH2 (Forward) |
| 1 | 1 | 0b | 0 | L | H | L | H | L | L | Low-Side Active Freewheel |
| 1 | 1 | 1b | 0 | H | L | H | L | H | H | High-Side Active Freewheel |
| X | X | X | 1 | L | L | L | L | HI-Z | HI-Z | High-Impedance |
| INPUT | OUTPUT | |||||||||
|---|---|---|---|---|---|---|---|---|---|---|
| IN3/EN2 | IN4/PH2 | FW2 | HIZ2 | GH3 | GL3 | GH4 | GL4 | SH3 | SH4 | DESCRIPTION |
| 0 | 0 | X | 0 | L | L | L | L | HI-Z | HI-Z | Diode Freewheel (Coast) |
| 0 | 1 | X | 0 | L | H | H | L | L | H | Drive SH4 → SH3 (Reverse) |
| 1 | 0 | X | 0 | H | L | L | H | H | L | Drive SH3 → SH4 (Forward) |
| 1 | 1 | 0b | 0 | L | H | L | H | L | L | Low-Side Active Freewheel |
| 1 | 1 | 1b | 0 | H | L | H | L | H | H | High-Side Active Freewheel |
| X | X | X | 1 | L | L | L | L | HI-Z | HI-Z | High-Impedance |
Figure 7-9 H-Bridge Control Example