ZHCSN08D August 2020 – April 2024 DRV8714-Q1 , DRV8718-Q1
PRODMIX
If at any time the power supply voltage on the PVDD pin falls below the VPVDD_UV threshold for longer than the tPVDD_UV_DG time, the DRV871x-Q1 detects a PVDD undervoltage condition. After detecting the undervoltage condition, the gate driver pull downs are enabled, charge pump disabled and nFAULT pin, FAULT register bit, and PVDD_UV register bit asserted.
On SPI device variants, the PVDD undervoltage monitor can recover in two different modes set through the PVDD_UV_MODE register setting.
On H/W device variants, the PVDD undervoltage monitor is fixed to automatic recovery mode.