ZHCSN08D August 2020 – April 2024 DRV8714-Q1 , DRV8718-Q1
PRODMIX
The high-side gate drive voltage for the external MOSFET is generated using a tripler (dual-stage) charge pump that operates from the PVDD voltage supply input. The charge pump allows the high-side and low-side gate drivers to properly bias the external N-channel MOSFETs with respect to its source voltage across a wide input supply voltage range. The charge pump output is regulated (VVCP) to maintain a fixed voltage respect to VPVDD. The charge pump is continuously monitored for an undervoltage (VCP_UV) event to prevent under driven MOSFET conditions or in case of a short circuit condition.
The charge pump provides several configuration options. By default the charge pump will automatically switch between tripler (dual-stage) mode and doubler (single-stage) mode after the PVDD pin voltage crosses the VCP_SO threshold in order to reduce power dissipation. On SPI device variants, the charge pump can also be configured to always remain in tripler or doubler mode through the SPI register setting CP_MODE.
The charge pumps requires a low ESR, 1-μF, 16-V ceramic capacitor (X5R or X7R recommended) between the PVDD and VCP pins to act as the storage capacitor. Additionally, a low ESR, 100-nF, PVDD-rated ceramic capacitor (X5R or X7R recommended) is required between the CP1H to CP1L and CP2H to CP2L pins to act as the flying capacitors.
Since the charge pump is regulated to the PVDD pin, it should be ensured that the voltage difference between the PVDD pin and MOSFET power supply is limited to a threshold that allows for proper VGS of the external MOSFET during switching operation.